ADAU1445 Analog Devices, ADAU1445 Datasheet - Page 45

• Manufacturer Part Number: ADAU1445
• Manufacturer: Analog Devices

Specifications of ADAU1445

• Instructions/cycles: 3584
• Digital I/o Channels: 24/24
• Analog I/o Channels: 0/0
• Product Description: Digital audio processor with flexible audio routing matrix, 8 × 2-channel ASRC

Clock Output Enable Bit (Bit 15)
This bit controls the serial port’s respective bit clock as well as
the left and right clocks. When this bit is set to 1, the clock pins
are set to output. When this bit is set to 0, the clock pins are not
output clocks. In Register 0xE040 to Register 0xE048, Bit 15 and
Bits[13:10] must be used in conjunction to set the port as a master
or slave. Clock domains are assigned to input or output serial
ports with the clock pad multiplexer register (Address 0xE240).
For more information, see the Clock Pad Multiplexer section.
Frame Sync Type Bit (Bit 14)
This bit sets the type of LRCLK signal that is used. When this
bit is set to 0, the clock signal is a square wave. When this bit is
set to 1, the signal is a narrow pulse.
Clock Domain Master/Slave Select Bits (Bits[13:10])
These bits set whether the serial port outputs its clocks as a
master or slave to an available clock domain. If a serial port is
set to be a master, the clock output enable bit (Bit 15) must be
set to 1. If a serial port is set as a slave, the clock output enable
bit (Bit 15) must be set to 0. In both cases, the corresponding
clock pad multiplexer must be set to the serial output domain if it
is assignable. For more information, see the Clock Pad Multiplexer
section. Note that an arbitrary number of serial ports can be
slaves to a single clock domain, but a single serial port can only
be a master to one clock domain. The values for f
and f
172.032 MHz core clock signal.
Serial Output BCLK Polarity Bit (Bit 9)
The polarity of BCLKx determines whether LRCLKx and
SDATA_OUTx change on a rising (+) or falling (−) edge of the
BCLKx signal. Standard I
Serial Output LRCLK Polarity Bit (Bit 8)
The polarity of LRCLKx determines whether the left stereo
channel is initiated on a rising (+) or falling (−) edge of the
S,QUAD
are 48 kHz, 96 kHz, and 192 kHz, respectively, for a
2
S signals use negative BCLK polarity.
BCLK POLARITY
LRCLK POLARITY
SDATA_OUTx
SDATA_OUTx
LRCLKx
LRCLKx
LRCLKx
LRCLKx
BCLKx
BCLKx
S,NORMAL
L
Figure 35. Serial Output LRCLK Polarity
Figure 34. Serial Output BCLK Polarity
, f
S,DUAL
R
Rev. C | Page 45 of 92
,
L
LRCLKx signal. Standard I
polarity.
Word Length Bits (Bits[7:6])
These bits set the word length of the input data at 16, 20, or
24 bits. The output stream always has space for 24 bits of data,
but if the word length is set lower, the extra bits are set as 0s. The
fourth setting is flexible TDM. For more information, see the
Serial Output Flexible TDM Interface Modes and Settings
section.
MSB Position Bits (Bits[5:3])
These bits set the position of the MSB in the data stream.
TDM Type Bits (Bits[2:0])
These bits set the number of channels contained in the data
stream. The possible choices are TDM2 (stereo), TDM4, TDM8
or flexible TDM, TDM16, and packed TDM4 mode. For more
information on the packed TDM4 mode, see the Packed TDM4
Mode section. If word length bits (Bits[7:6]) are set to 11 for
flexible TDM mode, then the TDM type bits (Bits[2:0]) must
also be set for flexible TDM mode (that is, set to 010).
High Speed Slave Interface Mode Register
(Address 0xE049)
Table 31. Bit Descriptions of Register 0xE049
Bit Position
[15:1]
0
High Speed Slave Interface Mode Bit (Bit 0)
If any of the serial output ports are slaves to a bit clock greater than
22 MHz, the high speed slave interface mode must be enabled.
R
ADAU1442/ADAU1445/ADAU1446
L
Description
Reserved
High speed slave interface mode
0 = disabled
1 = enabled
R
2
S signals use negative LRCLK
Default
0