ADAU1445 Analog Devices, ADAU1445 Datasheet - Page 62

• Manufacturer Part Number: ADAU1445
• Manufacturer: Analog Devices

Specifications of ADAU1445

• Instructions/cycles: 3584
• Digital I/o Channels: 24/24
• Analog I/o Channels: 0/0
• Product Description: Digital audio processor with flexible audio routing matrix, 8 × 2-channel ASRC

ADAU1442/ADAU1445/ADAU1446
RELIABILITY FEATURES
The ADAU1442/ADAU1445/ADAU1446 contain several
subsystems designed to increase the reliability of the system
in which they are used. When these functions are used in
conjunction with an external host controller device, the DSP
can recover from serious errors, such as memory corruption or
a program counter crash.
CRC Modes and Settings
Cyclic Redundancy Check (CRC) Registers
(Address 0xE200 to Address 0xE202)
Table 42. Register Details of CRC Registers
Decimal
57856
57857
57858
The CRC constantly checks the validity of the program RAM
contents. SigmaStudio generates a 32-bit hash sum when a
program is compiled that must be written to two consecutive
16-bit register locations. The CRC must then be enabled. Every
4096 frames (88 ms when f
its own 32-bit code and compares it with the one stored in these
registers. If they do not match, an MP pin is set high (CRC
flag). This output flag must be enabled using the output CRC
error sticky command in the multipurpose pin control register
(see the Multipurpose Pin Control Registers (Address 0xE204 to
Address 0xE20F) section).
The user turns this enable on when continuous CRC checking is
desired. This defaults to off and can be set high after the user
has loaded a program and sent the correct CRC, calculated by
SigmaStudio. If there is an error, it can be cleared by setting the
enable bit low, fixing the error (presumably by reloading the
program) and then setting it high again.
Address
Hex
E200
E201
E202
CRC enable
Register
CRC Ideal
Value 1
CRC Ideal
Value 2
S,NORMAL
Function
16 MSBs of the
CRC hash sum
16 LSBs of the CRC
hash sum
1-bit CRC enable,
active high
is 48 kHz), the IC generates
Default
0
0
0
Rev. C | Page 62 of 92
The CRC control registers are configured as follows:
•
•
•
The CRC error sticky register is a single-bit read-only register at
Address 57893 (Address 0xE225) that acts as the CRC error
flag. It can optionally be sent to an MP pin. For example, it can
connect to an interrupt pin on an external microcontroller,
which triggers a rewrite of the corrupted memory. The register
is reset when the CRC enable register goes low.
CRC Error Sticky Register (Address 0xE225)
Table 43. Bit Description of Register 0xE225
Bit Position
[15:1]
0
This single-bit read-only register goes high when there is a CRC
error. It is reset to 0 when the CRC enable is reset to 0.
CRC Ideal Value 1 is the 16 MSBs of the CRC code.
CRC Ideal Value 2 is the 16 LSBs of the CRC code.
CRC enable is a 1-bit enable.
Description
Reserved
CRC error sticky (read only)
Default
0