ADAU1445 Analog Devices, ADAU1445 Datasheet - Page 26

• Manufacturer Part Number: ADAU1445
• Manufacturer: Analog Devices

Specifications of ADAU1445

• Instructions/cycles: 3584
• Digital I/o Channels: 24/24
• Analog I/o Channels: 0/0
• Product Description: Digital audio processor with flexible audio routing matrix, 8 × 2-channel ASRC

ADAU1442/ADAU1445/ADAU1446
CONTROL PORT
Overview
The ADAU1442/ADAU1445/ADAU1446 can operate in one of
three control modes: I
self-boot mode (no external controller).
The ADAU1442/ADAU1445/ADAU1446 have both a 4-wire
SPI control port and a 2-wire I
used to set the RAMs and registers. When the SELFBOOT pin
is low at power-up, the chip defaults to I
into SPI control mode by pulling Pin CLATCH low three times.
When the SELFBOOT pin is set high at power-up, the ADAU1442/
ADAU1445/ADAU1446 load the program, parameters, and
register settings from an external EEPROM at startup.
The control port is capable of full read and write operations for
all memories and registers, except for those that are read only.
Most signal processing parameters are controlled by writing
new values to the parameter RAM using the control port. Other
functions, such as mute and input/output mode control, are
programmed by writing to the registers.
All addresses can be accessed in either a single-word mode or a
burst mode. A control word consists of the chip address, the
register/RAM subaddress, and the data to be written. The
number of bytes per word depends on the type of data that is
being written.
The first byte (Byte 0) of a control word contains the 7-bit chip
address plus the R/ W bit. The next two bytes (Byte 1 and Byte 2)
together form the subaddress of the memory or register location
within the ADAU1442/ADAU1445/ADAU1446. This subaddress
must be two bytes because the memory locations within the
ADAU1442/ADAU1445/ADAU1446 are directly addressable,
and their sizes exceed the range of single-byte addressing. All
subsequent bytes (starting with Byte 3) contain the data, such as
control port data, program data, or parameter data. The exact
formats for specific types of writes are shown in
Figure 19
The ADAU1442/ADAU1445/ADAU1446 have several
mechanisms for updating signal processing parameters in real
time without causing pops or clicks in the output. In cases
where large blocks of data must be downloaded, the output of
the DSP core can be halted, new data can be loaded, and then
the output of the DSP core can be restarted. This is typically
done during the booting sequence at startup or when loading a
new program into RAM. In cases where only a few parameters
must be changed, they can be loaded without halting the program.
A software-based safeload mechanism is included for this purpose,
and it can be used to buffer a full set of parameters (for example,
the five coefficients of a biquad) and then transfer these parameters
into the active program within one audio frame.
The control port pins are multifunctional according to the mode in
which the part is operating. Table 16 details these functions.
.
2
C control mode, SPI control mode, or
2
C bus control port. Each can be
2
C mode but can be put
Figure 13
and
Rev. C | Page 26 of 92
I
The ADAU1442/ADAU1445/ADAU1446 support a 2-wire
serial (I
peripherals. Two pins, serial data (SDA) and serial clock (SCL),
carry information between the ADAU1442/ADAU1445/
ADAU1446 and the system I
the ADAU1442/ADAU1445/ADAU1446 are always slaves on the
bus, which means that the parts cannot initiate a data transfer.
Each slave device is recognized by a unique address. The address
bit sequence is shown in Table 13. The ADAU1442/ADAU1445/
ADAU1446 have eight possible slave addresses: four for writing
operations and four for reading. These are unique addresses for
the device and are listed in Table 14.
Users can communicate with these addresses by using the USBi
communication channel list in the hardware configuration tab
of SigmaStudio. The LSB of the byte sets either a read or write
operation; Logic Level 1 corresponds to a read operation, and
Logic Level 0 corresponds to a write operation. Address Bit 5 and
Address Bit 6 are set by tying the ADDRx pins of the ADAU1442/
ADAU1445/ADAU1446 to Logic Level 0 or Logic Level 1. Both
SDA and SCL should have pull-up resistors on the lines connected
to them (a standard value is 2.0 kΩ, but this can be changed
depending on the capacitive load on the line). The voltage on
these signal lines should not be greater than the voltage of
IOVDD (3.3 V).
Table 13. ADAU1442/ADAU1445/ADAU1446 Address Bit
Sequence
Bit 0
0
Table 14. ADAU1442/ADAU1445/ADAU1446 I
Addresses
ADDR1
0
0
0
0
1
1
1
1
1
Addressing
Initially, all devices on the I
the devices monitor the SDA and SCL lines for a start condition
and the proper address. The I
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address or
an address and data stream follow. All devices on the bus respond
to the start condition and shift the next eight bits (7-bit address
+ R/ W bit) MSB first. The device that recognizes the transmitted
2
0 = write, 1 = read.
C Port
2
Bit 1
1
C-compatible) microprocessor bus driving multiple
ADDR0
0
0
1
1
0
0
1
1
Bit 2
1
Read/Write
0
1
0
1
0
1
0
1
Bit 3
1
2
2
C bus are in an idle state, in which
2
C master initiates a data transfer by
C master controller. In I
Bit 4
0
1
Slave Address
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
Bit 5
ADDR1
Bit 6
ADDR0
2
C Slave
2
C mode,
Bit 7
R/W