ADAU1445 Analog Devices, ADAU1445 Datasheet - Page 8

• Manufacturer Part Number: ADAU1445
• Manufacturer: Analog Devices

Specifications of ADAU1445

• Instructions/cycles: 3584
• Digital I/o Channels: 24/24
• Analog I/o Channels: 0/0
• Product Description: Digital audio processor with flexible audio routing matrix, 8 × 2-channel ASRC

ADAU1442/ADAU1445/ADAU1446
DIGITAL TIMING SPECIFICATIONS
T
Table 4.
Parameter
MASTER CLOCK
CORE CLOCK
SERIAL PORT
SPI PORT
I
MULTIPURPOSE PINS AND RESET
1
2
2
All timing specifications are given for the default (I
Maximum SPI CCLK clock frequency is dependent on current drive strength and capacitive loads on the circuit board.
C PORT
A
f
t
t
CLKOUT Jitter
f
f
t
t
t
t
t
t
t
t
t
t
f
f
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
f
t
t
= −40°C to +105°C, DVDD = 1.8 V, IOVDD = 3.3 V.
MP
MP
MD
CORE
BCLK
BCLK
BIL
BIH
LIS
LIH
SIS
SIH
TS
SODS
SODM
CCLK write
CCLK read
CCPL
CCPH
CLS
CLH
CLPH
CLDLY
CDS
CDH
COV
SCL
SCLH
SCLL
SCS
SCH
DS
DH
SCLR
SCLF
SDR
SDF
BFT
MP
MPIL
RLPW
1
Min
2.822
40.69
25
40.69
30
30
20
20
10
10
20
20
0
35
20
20
0
35
0.6
1.3
0.6
0.6
100
0.9
1.3
10
2
S) states of the serial audio input ports and the serial audio output ports (see Table 26 and Table 30).
Max
24.576
354.36
75
250
172.032
24.576
5
30
30
32
16
40
400
300
300
300
300
f
1.5 × 1/f
S
/2
S,NORMAL
Rev. C | Page 8 of 92
Unit
MHz
ns
%
ps
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
ns
μs
ns
ns
ns
ns
μs
Hz
μs
ns
Description
Master clock (MCLK) frequency. See the Master Clock and PLL section.
Master clock (MCLK) period. See the
Master clock (MCLK) duty cycle.
Cycle-to-cycle rms average.
DSP core clock frequency.
BCLK frequency.
BCLK period.
BCLKx low pulse width, slave mode.
BCLKx high pulse width, slave mode.
LRCLKx setup to BCLKx input rising edge, slave mode.
LRCLKx hold from BCLKx input rising edge, slave mode.
SDATA_INx setup to BCLKx input rising edge.
SDATA_INx hold from BCLKx input rising edge.
BCLKx output falling edge to LRCLKx output timing skew.
SDATA_OUTx delay in slave mode from BCLKx output falling edge.
SDATA_OUTx delay in master mode from BCLKx output falling edge.
CCLK frequency.
CCLK frequency.
CCLK pulse width low.
CCLK pulse width high.
CLATCH setup to CCLK rising edge.
CLATCH hold from CCLK rising edge.
CLATCH pulse width high.
Minimum delay between CLATCH low pulses.
CDATA setup to CCLK rising edge.
CDATA hold from CCLK rising edge.
COUT valid output delay from CCLK falling edge.
SCL clock frequency.
SCL pulse width high.
SCL pulse width low.
Start and repeated start condition setup time.
Start condition hold time.
Data setup time.
Data hold time.
SCL rise time.
SCL fall time.
SDA rise time.
SDA fall time.
Bus-free time between stop and start.
MPx maximum switching rate.
MPx pin input latency until high/low value is read by core. Guaranteed by
design.
RESET low pulse width.
2
2
Master Clock and PLL
section.