ADAU1445 Analog Devices, ADAU1445 Datasheet - Page 29

• Manufacturer Part Number: ADAU1445
• Manufacturer: Analog Devices

Specifications of ADAU1445

• Instructions/cycles: 3584
• Digital I/o Channels: 24/24
• Analog I/o Channels: 0/0
• Product Description: Digital audio processor with flexible audio routing matrix, 8 × 2-channel ASRC

SPI Port
By default, the ADAU1442/ADAU1445/ADAU1446 are in I
mode, but these parts can be put into SPI control mode by pulling
CLATCH low three times. Each low pulse should have a minimum
duration of 20 ns, and the delay between pulses should be at
least 20 ns.
The SPI port uses a 4-wire interface, consisting of CLATCH,
CCLK, CDATA, and COUT signals. The CLATCH signal goes
low at the beginning of a transaction and high at the end of a
transaction. The CCLK signal latches CDATA on a low-to-high
transition. COUT data is shifted out of the ADAU1442/
ADAU1445/ADAU1446 on the falling edge of CCLK and should
be clocked into a receiving device, such as a microcontroller, on
the next CCLK falling edge (rising edge is possible if t
is met). The CDATA signal carries the serial input data, and the
COUT signal is the serial output data. The COUT signal remains
three-stated until a read operation is requested. This allows
other SPI-compatible peripherals to share the same readback
line. All SPI transactions have the same word sequence shown
in Table 15 (see Figure 4 for an SPI port timing diagram). All
data written should be MSB first.
Chip Address R/ W
The first byte of an SPI transaction includes the 7-bit chip address
and a R/ W bit. The chip address is set by the ADDR0 pin. This
Table 15. Generic Control Word Sequence
Byte 0
Chip Address[6:0], R/W
1
Continues to end of data.
CLATCH
CDATA
CCLK
CLATCH
CDATA
COUT
CCLK
BYTE 0
Byte 1
Subaddress[15:8]
HIGH-Z
BYTE 0
Figure 19. SPI Write Clocking (Single-Write Mode)
Figure 20. SPI Read Clocking (Single-Read Mode)
BYTE 1
COV
timing
2
C
Rev. C | Page 29 of 92
BYTE 2
Byte 2
Subaddress[7:0]
allows two ADAU1442/ADAU1445/ADAU1446 devices to share
a CLATCH signal, yet still operate independently. When ADDR0 is
low, the chip address is 0000000; when ADDR0 is high, the address
is 0000001. The LSB of the first byte determines whether the SPI
transaction is a read (Logic Level 1) or a write (Logic Level 0).
Users can communicate with both ICs with up to five latch
signals by using the USBi communication channel list in the
hardware configuration tab in SigmaStudio.
Subaddress
The 16-bit subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate RAM location or register.
Data Bytes
The number of data bytes varies according to the register
or memory being accessed. In burst write mode, an initial
subaddress is given followed by a continuous sequence of data
for consecutive memory or register locations.
A sample timing diagram for a single SPI write operation to
the parameter RAM is shown in Figure 19. A sample timing
diagram of a single SPI read operation is shown in Figure 20.
The COUT pin goes from three-state to driven at the beginning
of Byte 3. In this example, Byte 0 to Byte 2 contain the addresses
and R/ W bit, and subsequent bytes carry the data.
BYTE 1
DATA
ADAU1442/ADAU1445/ADAU1446
BYTE 2
Byte 3
Data
DATA
BYTE 3
HIGH-Z
Byte 4
Data
1