LPC1850FET256 NXP Semiconductors, LPC1850FET256 Datasheet - Page 113

• Manufacturer Part Number: LPC1850FET256
• Description: The LPC1850FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 17.
C
2.7 V
[1]
[2]
[3]
[4]
[5]
LPC1850_30_20_10
Preliminary data sheet
Symbol
t
t
t
t
BLSHDNV
CSHEOW
BLSHDNV
WEHANV
Fig 29. External static memory read/write access (PB = 0)
L
= 22 pF for EMC_Dn C
Parameters specified for 40 % of V
T
End Of Read (EOR): longest of t
Start Of Read (SOR): longest of t
End Of Write (EOW): earliest of address not valid or EMC_BLSn HIGH.
cy(clk)

V
DD(IO)
= 1/CCLK (see LPC18xx User manual).
Dynamic characteristics: Static external memory interface
EMC_BLSn
Parameter
BLS HIGH to data invalid
time
CS HIGH to end of write
time
BLS HIGH to data invalid
time
WE HIGH to address invalid
time
EMC_CSn
EMC_WE
EMC_OE
EMC_An
EMC_Dn

3.6 V; values guaranteed by design.
[1]
L
= 20 pF for all others; T
CSHOEH
CSLAV
DD(IO)
, t
t
CSLOEL
, t
CSLOEL
for rising edges and 60 % of V
OEHANV
t
t
CSLSOR
Conditions
PB = 0
PB = 1
PB = 1
CSLAV
All information provided in this document is subject to legal disclaimers.
, t
, t
CSLBLSL
Rev. 3.1 — 15 December 2011
CSHBLSH
amb
SOR
.
=
t
t
OELOEH
am
.

[5]
40
[2]

Min
2.5 + T
2.0
2.5
0.9 + T
C to 85
DD(IO)
cy(clk)
cy(clk)

C; 2.2 V
EOR
t
t
OEHANV
CSHOEH
for falling edges.
t
CSHEOR
…continued
t
h(D)
32-bit ARM Cortex-M3 microcontroller
t
t

CSLBLSL
CSLDV
Typ
-
-
-
-
V
LPC1850/30/20/10
DD(REG)(3V3)
t
t
BLSLBLSH
CSLAV
t

BLSHDNV
EOW
3.6 V;
t
Max
1.4 + T
0
1.4
2.4 + T
BLSHEOW
© NXP B.V. 2011. All rights reserved.
t
002aag699
CSHEOW
cy(clk)
cy(clk)
113 of 157
Unit
ns
ns
ns
ns