LPC1850FET256 NXP Semiconductors, LPC1850FET256 Datasheet - Page 89
LPC1850FET256
Manufacturer Part Number
LPC1850FET256
Description
The LPC1850FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1810FBD144.pdf
(157 pages)
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NXP Semiconductors
LPC1850_30_20_10
Preliminary data sheet
Fig 11. LPC1850/30/20/10 power domains
USB0_VDDA3V3_DRIVER
7.19 Emulation and debugging
USB0_VDDA3V3
The LPC1850/30/20/10 support four reduced power modes: Sleep, Deep-sleep,
Power-down, and Deep power-down.
The LPC1850/30/20/10 can wake up from Deep-sleep, Power-down, and Deep
power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery
powered blocks in the RTC power domain.
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four
watch points.
VDDREG
RTCX1
RTCX2
VDDIO
VDDA
VBAT
VSSA
VPP
VSS
LPC18xx
All information provided in this document is subject to legal disclaimers.
USB0 POWER DOMAIN
OTP POWER DOMAIN
ALWAYS-ON/RTC POWER DOMAIN
ADC POWER DOMAIN
MAIN POWER DOMAIN
SELECTOR
Rev. 3.1 — 15 December 2011
OSCILLATOR
POWER
to I/O pads
32 kHz
to RTC I/O
REGULATOR
pads (V
ps )
ULTRA LOW-POWER
REGULATOR
OTP
USB0
DAC
ADC
BACKUP REGISTERS
REAL-TIME CLOCK
RESET/WAKE-UP
CONTROL
32-bit ARM Cortex-M3 microcontroller
to core
to memories,
peripherals,
oscillators,
PLLs
LPC1850/30/20/10
to RTC
domain
peripherals
002aag305
RESET
WAKEUP0/1/2/3
ALARM
© NXP B.V. 2011. All rights reserved.
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