ST72334N4 STMicroelectronics, ST72334N4 Datasheet - Page 126

• Manufacturer Part Number: ST72334N4
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72334N4

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes

ST72334J/N, ST72314J/N, ST72124J
EMC CHARACTERISTICS (Cont’d)
16.7.3 ESD Pin Protection Strategy
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in
pins and in
drain pins.
Figure 77. Positive Stress on a Standard Pad vs. V
Figure 78. Negative Stress on a Standard Pad vs. V
126/153
Main path
Path to avoid
Main path
Figure 79
Figure 77
V
V
V
V
DD
DD
SS
SS
and
and
Figure 80
Figure 78
(3a)
(3b)
(3a)
(3b)
for true open
for standard
OUT
OUT
SS
Standard Pin Protection
To protect the output structure the following ele-
ments are added:
To protect the input structure the following ele-
ments are added:
DD
– A diode to V
– A protection device between V
– A resistor in series with the pad (1)
– A diode to V
– A protection device between V
(4)
(4)
IN
IN
DD
DD
(3a) and a diode from V
(2a) and a diode from V
(2a)
(2b)
(2a)
(2b)
(1)
(1)
DD
DD
and V
and V
SS
SS
SS
SS
V
V
V
V
DD
SS
DD
SS
(3b)
(2b)
(4)
(4)