ST72334N4 STMicroelectronics, ST72334N4 Datasheet - Page 47

• Manufacturer Part Number: ST72334N4
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72334N4

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes

MISCELLANEOUS REGISTERS (Cont’d)
13.3 REGISTERS DESCRIPTION
MISCELLANEOUS REGISTER 1 (MISCR1)
Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
ei2 (port B3..0) and ei3 (port B7..4). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled
1: MCO alternate function enabled
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
IS11
(I/O pin free for general-purpose I/O)
(f
7
OSC
External Interrupt Sensitivity
IS10 MCO IS21
/2 on I/O port)
IS20
CP1
CP0
IS11 IS10
0
0
1
1
SMS
0
0
1
0
1
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:-
ei0 (port A3..0) and ei1 (port F2..0). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).
Bit 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f
See low power consumption mode and MCC
chapters for more details.
f
f
f
f
OSC
OSC
OSC
OSC
/ 4
/ 8
/ 16
/ 32
ST72334J/N, ST72314J/N, ST72124J
f
CPU
in SLOW mode
CPU
CPU
is given by CP1, CP0
=
f
OSC
/ 2
CP1 CP0
0
1
0
1
47/153
0
0
1
1