ST72334N4 STMicroelectronics, ST72334N4 Datasheet - Page 27

• Manufacturer Part Number: ST72334N4
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72334N4

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes

9.1 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detec-
tor function (LVD) generates a static reset when
the V
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.
The V
than the V
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
V
The LVD function is illustrated in the
Provided the minimum V
the oscillator frequency) is above V
can only be in two modes:
Figure 13. Low Voltage Detector vs Reset
DD
– V
– V
– under full software control
– in static safe reset
RESET
is below:
DD
IT-
IT+
IT-
V
V
IT-
IT+
reference value for a voltage drop is lower
when V
supply voltage is below a V
when V
IT+
reference value for power-on in order
V
DD
DD
DD
is falling
is rising
DD
value (guaranteed for
Figure
IT-
IT-
, the MCU
reference
13.
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
1. The LVD allows the device to be used without
any external RESET circuitry.
2. Three different reference levels are selectable
through the option byte according to the applica-
tion requirement.
LVD application note
Application software can detect a reset caused by
the LVD by reading the LVDRF bit in the CRSR
register.
This bit is set by hardware when a LVD reset is
generated and cleared by software (writing zero).
V
hyst
ST72334J/N, ST72314J/N, ST72124J
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