ST72334N4 STMicroelectronics, ST72334N4 Datasheet - Page 53

• Manufacturer Part Number: ST72334N4
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72334N4

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d)
MISCELLANEOUS REGISTER 1 (MISCR1)
See
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read /Write
Reset Value: 0000 0001 (01h)
Bit 7:4 = Reserved, always read as 0.
Bit 3:2 = TB[1:0] Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid unwanted time shift. This allows to
use this time base as a real time clock.
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt allows to exit from ACTIVE-HALT
mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode
Table 13. MCC Register Map and Reset Values
Prescaler
Counter
Address
160000
400000
7
0
32000
64000
(Hex.)
0029h
Section 13 on page
.
0
f
OSC
MCCSR
Reset Value
Register
20ms
50ms
0
4ms
8ms
Label
=8MHz f
Time Base
0
46.
OSC
TB1
10ms
25ms
=16MHz
2ms
4ms
7
0
TB0
TB1
6
0
OIE
0
0
1
1
TB0
OIF
0
0
1
0
1
5
0
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has measured the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
14.2.4 Low Power Modes
14.2.5 Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
Note:
1. The MCC/RTC interrupt allows to exit from AC-
TIVE-HALT mode, not from HALT mode.
WAIT
ACTIVE-
HALT
HALT
Time base overflow
event
Mode
Interrupt Event
4
0
ST72334J/N, ST72314J/N, ST72124J
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
No effect on MCC/RTC counter (OIE bit is
set), the registers are frozen.
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
TB1
3
0
Event
Flag
OIF
TB0
2
0
Description
Control
Enable
OIE
Bit
OIE
1
0
from
Wait
Exit
Yes
OIF
from
No
53/153
Halt
Exit
0
1
1)