ST72334N4 STMicroelectronics, ST72334N4 Datasheet - Page 38

• Manufacturer Part Number: ST72334N4
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72334N4

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes

ST72334J/N, ST72314J/N, ST72124J
POWER SAVING MODES (Cont’d)
11.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see
TROLLER WITH REAL TIME CLOCK TIMER
(MCC/RTC)" on page 52
MCCSR register).
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see
mapping,” on page
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 18.1 on page 144
Figure 24. HALT Timing Overview
38/153
[MCCSR.OIE=0]
INSTRUCTION
RUN
HALT
HALT
Section 14.2 "MAIN CLOCK CON-
4096 CPU CYCLE
34) or a RESET. When exiting
INTERRUPT
RESET
DELAY
OR
for more details on the
for more details).
Table 5, “Interrupt
VECTOR
FETCH
Figure
RUN
25).
Figure 25. HALT Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
N
HALT INSTRUCTION
WATCHDOG
WDGHALT
Table 5, “Interrupt mapping,” on page 34
(MCCSR.OIE=0)
RESET
1
INTERRUPT
Y
1)
3)
ENABLE
4096 CPU CLOCK CYCLE
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I BIT
I BIT
I BITS
N
DELAY
RESET
Y
WATCHDOG
DISABLE
2)
OFF
OFF
OFF
OFF
ON
ON
X
ON
ON
ON
X
0
4)
4)
for