ST72334N4 STMicroelectronics, ST72334N4 Datasheet - Page 29

• Manufacturer Part Number: ST72334N4
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72334N4

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes

RESET SEQUENCE MANAGER (Cont’d)
9.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least t
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least t
Figure 16. RESET Sequences
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
V
V
IT+
IT-
Figure
RUN
V
DD
16).
ON
DELAY
RESET
weak pull-up resistor.
LVD
w(RSTL)out
.
t
t
h(RSTL)in
w(RSTL)out
h(RSTL)in
RUN
in
DELAY
SHORT EXT.
RESET
9.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
The device RESET pin acts as an output that is
V
The LVD filters spikes on V
avoid parasitic resets.
9.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
low during at least t
pulled low when V
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
DD
t
Power-On RESET
Voltage Drop RESET
h(RSTL)in
<V
RUN
ST72334J/N, ST72314J/N, ST72124J
IT-
(falling edge) as shown in
WATCHDOG UNDERFLOW
DELAY
LONG EXT.
RESET
w(RSTL)out
DD
<V
RUN
DD
IT+
INTERNAL RESET (4096 T
FETCH VECTOR
.
larger than t
DELAY
(rising edge) or
WATCHDOG
RESET
t
w(RSTL)out
Figure
Figure
g(VDD)
16.
RUN
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CPU
16.
to
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