S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 17

• Manufacturer Part Number: S1D13700F02
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 2005/11/29
Pin Name Type Pin #
SCANEN
RESET#
TSTEN
WAIT#
WR#
CS#
AS#
O
I
I
I
I
I
I
42
43
54
61
36
37
38
HTB2T
CID1
Cell
T1
SI
SI
CI
SI
Table 5-2 Host Interface Pin Descriptions
HIOVDD
HIOVDD
HIOVDD
HIOVDD
HIOVDD
HIOVDD
HIOVDD
Power
Power On
RESET#/
State
—
—
—
—
—
—
Z
Revision 1.01
This input pin has multiple functions.
Chip select.
This active-low input enables the S1D13700F02. It is usually
connected to the output of an address decoder device that
maps the S1D13700F02 into the memory space of the
controlling microprocessor.
This output pin has multiple functions.
This input pin has multiple functions.
This active-low input performs a hardware reset of the
S1D13700F02 which sets all internal registers to their default
states and forces all signals to their inactive states.
Note: Do not trigger a RESET# when the supply voltage is
lowered.
Reserved
This pin must be connected to ground (VSS).
Reserved
This pin must be connected to ground (VSS).
• When the Generic host bus interface is selected, this
• When the M6800 host bus interface is selected, this signal
• When the MC68K host bus interface is selected, this
• When the Generic host bus interface is selected, this pin is
• When the MC68K host bus interface is selected, this pin is
• When the M6800 host bus interface is selected, this pin
• When the Generic host bus interface is selected, this pin
• When the MC68K host bus interface is selected, this pin is
• When the M6800 host bus interface is selected, this pin
signal is the active-low write strobe (WR#). The bus data
is latched on the rising edge of this signal.
is the read/write control signal (R/W#). Data is read from
the S1D13700F02 if this signal is high, and written to the
S1D13700F02 if it is low.
signal is the read/write control signal (RD/WR#). Data is
read from the S1D13700F02 if this signal is high, and
written to the S1D13700F02 if it is low.
WAIT#. During a data transfer, WAIT# is driven active-low
to force the system to insert wait states. It is driven
inactive to indicate the completion of a data transfer.
WAIT# is released to a high impedance state after the
data transfer is complete. For indirect addressing mode,
the WAIT# pin can be used to handshake with the Host.
DTACK#. During a data transfer, DTACK# is driven active-
high to force the system to insert wait states. It is driven
inactive to indicate the completion of a data transfer.
DTACK# is released to a high impedance state after the
data transfer is complete. For indirect addressing mode,
the DTACK# pin can be used to handshake with the Host.
must be left unconnected and floating.
must be connected to VDD (pulled high).
the address strobe (AS#).
must be connected to VDD (pulled high).
Description
X42D-A-001-01
S1D13700F02
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