S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 58
S1D13700F02
Manufacturer Part Number
S1D13700F02
Description
Embedded Memory Graphics Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13700F02.pdf
(130 pages)
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S1D13700F02
X42D-A-001-01
REG[00h] bit 3
REG[00h] bit 3
(W/S)
(W/S)
0
0
Three-Layer Configuration
Note
Second Screen Block
First Screen Block
SAD1
1
2
3
SL1
SAD2
The size of screen block 3, in lines, is automatically set to the size of the screen
block with the least number of lines (either SL1 or SL2).
The parameters corresponding to SL3 and SL4 are fixed by REG[05h] bits 7-0
(L/F) and do not have to be set.
If a dual panel is selected (REG[00h] bit 3 = 1), the differences between SL1 and
(L/F + 1) ÷ 2, and between SL2 and (L/F + 1) ÷ 2, are blanked.
Screen
Screen
Graphics display
page 1
Layer 1
SAD1
Table 10-7 Display Modes (Continued)
SL1
SAD2
SAD3
Screen Configuration Example
Layer 1
Graphics display
page 1
Set SL1 > SL2
Screen Configuration Example
Revision 1.01
Layer 2
SL1 = L/F + 1
First Layer
First Layer
SAD1, SL1
SAD1,
—
Layer 2
Graphics display page 2
Graphics display page 3
Layer 3
(SAD3)
SL2
Graphics display page 3
Graphics display page 2
SAD3 (see note 2)
Second Layer
Second Layer
SL2 = L/F + 1
SAD2, SL2
SAD2,
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 2005/11/29
Third Layer
SAD3
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