S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 27

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S1D13700F02

Manufacturer Part Number
S1D13700F02
Description
Embedded Memory Graphics Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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Epson Research and Development
Vancouver Design Center
1. Ts
2. t4min
3. t11max = 1Ts + 5 (for 3.3V)
4. t12min = 1Ts (for a read cycle followed by a read or write cycle)
5. t13max = 4Ts + 2
Hardware Functional Specification
Issue Date: 2005/11/29
Symbol
t10
t11
t12
t13
t1
t2
t3
t4
t5
t6
t7
t8
t9
CS# setup time
A[15:0] setup time
WR#, RD# falling edge to WAIT# driven low
D[7:0] setup time to WR# rising edge (write cycle)
RD# falling edge to D[7:0] driven (read cycle)
CS# hold time
A[15:0] hold time
RD#, WR# rising edge to WAIT# high impedance
D[7:0] hold time from WR# rising edge (write cycle)
D[7:0] hold time from CS# rising edge (read cycle)
WAIT# rising edge to valid Data
RD#, WR# pulse inactive time
WAIT# pulse active time
= System clock period
= 2Ts + 5
= 1Ts + 7 (for 5.0V)
= 2Ts + 2 (for a write cycle followed by a write cycle)
= 5Ts + 2 (for a write cycle followed by a read cycle)
Table 7-3 Generic Bus Direct/Indirect Interface with WAIT# Timing
Parameter
Revision 1.01
Note 2
Note 4
Min
5
5
2
3
7
7
2
5
3
3.3 Volt
Note 3
Note 5
Max
15
10
14
Note 2
Note 4
Min
5
5
2
3
7
7
2
5
3
5.0 Volt
Note 3
Note 5
Max
X42D-A-001-01
15
10
14
S1D13700F02
Page 27
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