S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 36

• Manufacturer Part Number: S1D13700F02
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 36
7.4 Power Save Mode/Display Enable Timing
1. Ts
2. Power Save Mode is controlled by the Power Save Mode Enable bit, REG[08h] bit 0.
3. Display On/Off is controlled by the Display Enable bit, REG[09h] bit 0.
S1D13700F02
X42D-A-001-01
Symbol
t1a
t1b
t1c
t2
*LCD Signals include: FPDAT[3:0], FPSHIFT, FPLINE, FPFRAME, MOD, and XECL.
LCD Signals*
YDIS falling edge delay for Power Save Mode
Enable in Indirect Mode (see Note 2)
YDIS falling edge delay for Display Off in Indirect
Mode (58h)
YDIS falling edge delay for Display Off in Direct
Mode (see Note 3)
YDIS rising edge delay for Display On (see Note 3)
= System Clock Period
YSCL
YDIS
WR#
Note
When using an external crystal with the internal oscillator, a delay is required after exit-
ing power save mode for system stabilization. For further information, refer to Section
7.2, “Reset Timing” on page 25.
Parameter
Figure 7-9 Power Save Mode/Display Enable Timing
Table 7-8 Power Save Mode/Display Enable Timing
Display On
t1
Display Off or Power Save Mode Enabled
Revision 1.01
Min.
⎯
⎯
⎯
⎯
3.0 Volt
1Ts + 10
2Ts + 10
2Ts + 10
Max.
2
t2
Display On
Epson Research and Development
Min.
⎯
⎯
⎯
⎯
Hardware Functional Specification
5.0 Volt
Vancouver Design Center
1Ts + 10
2Ts + 10
2Ts + 10
Issue Date: 2005/11/29
Max.
2
Frames
Units
ns
ns
ns