XA-SCC NXP Semiconductors, XA-SCC Datasheet - Page 30

• Manufacturer Part Number: XA-SCC
• Description: Cmos 16-bit Communications Microcontroller
• Manufacturer: NXP Semiconductors

1. On a 16 bit bus, if only one byte is being written, then only one of BLE_CASL or BHE_CASH will go active. On an 8 bit bus, BLE_CASL
2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all generic reads and fetches, in order to
3. To avoid tri-state fights during read cycles and fetch cycles, do not drive data bus until OE goes active
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS (3.3V
V
NOTES:
1999 Feb 23
All Cycles
All DRAM cycles
Generic Data Read Only
Data Read and Instruction Fetch Cycles
Write Cycles
Refresh
Wait Input
DD
CMOS 16-bit communications microcontroller
SYMBOL
goes active for all (odd or even address) accesses. BHE_CASH will not go active during any accesses on an 8 bit bus.
meet hold time, the slave device should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the
address changes. On all FPM DRAM reads and fetches, hold data valid on the bus until the earliest of RAS, CAS, or OE goes high
(inactive.) On all EDO DRAM reads and fetches, hold data valid on the bus until a new CAS is asserted, or until OE goes high (inactive.)
t
= 3.3V
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CODH
CPWH
CPWL
OHDE
CHCX
CLCH
CHCL
CHAH
CHAV
CHSH
AHDR
CHDV
SHAH
SHDH
CLCX
AVSL
CHSL
DVSL
CLRL
t
t
t
t
t
F
DIH
DIS
WS
WH
t
RP
C
C
10%, T
13, 14, 16,
12–14, 16,
10, 12, 13,
20, 21, 22
17, 20, 21
16, 20, 21
FIGURE
13, 21
11, 16
9, 10,
9, 16
25
25
25
25
25
25
All
All
All
All
All
26
24
21
24
24
amb
= –40 C to +85 C (industrial)
System Clock (internally called CClk) Frequency
System Clock Period = 1/FC
XTALIN High Time
XTALIN Low Time
XTALIN Rise Time
XTALIN Fall Time
Address Valid to Strobe low
Address hold after CLKOUT rising edge
Delay from CLKOUT rising edge to address valid
Delay from CLKOUT rising edge to Strobe High
Delay from CLKOUT rising edge to Strobe Low
ClkOut Duty Cycle High (into 40pF max.)
(See Warning Note 5 on page 31.)
CAS Pulse Width High
CAS Pulse Width Low
RAS precharge time, thus minimum RAS high time
Address hold (A19–A1 only, not A0) after CS, BLE, BHE rise at end
of Generic Data Read Cycle (not code fetch)
Data In Valid setup to ClkOut rising edge
Data In Valid hold after ClkOut rising edge
OE high to XA Data Bus Driver Enable
Clock High to Data Valid
Data Valid prior to Strobe Low
Minimum Address Hold Time after strobe goes inactive
Data hold after strobes (CS and BHE/BLE) high
CAS low to RAS low
WAIT setup (stable high or low) prior to CLKOUT rising edge
WAIT hold (stable high or low) after CLKOUT rising edge
PARAMETER
10%)
9
2
30
9
9
8
(n * t
t
t
t
t
t
t
t
t
t
t
t
CHCX
note 8
t
C
C
C
C
C
C
C
C
33.33
C
C
MIN
C
* 0.5
* 0.4
32
25
– 21
– 12
– 10
C
– 19
– 23
– 25
– 25
– 15
0
–
–
–
1
1
–12
0
–
0
1
) –16
–7
LIMITS
t
CHCX
MAX
Preliminary specification
30
30
28
25
30
–
–
–
5
5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+3
XA-SCC
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns