MC56F8346 Freescale Semiconductor, Inc, MC56F8346 Datasheet - Page 119

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MC56F8346

Manufacturer Part Number
MC56F8346
Description
56f8300 16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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6.5.8
The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate peripherals
for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B (NOT available in the 56F8146
device); these peripherals work together.
The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad Timer B, or as
SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown in
Figure 6-10
choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and in conjunction
with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function
of GPIOC[3:0] to be programmed as decoder functions. This can be changed by altering the appropriate
controls in the indicated registers.
Freescale Semiconductor
Preliminary
GPIO Peripheral Select Register (SIM_GPS)
and
Figure 6-10 Overall Control of Pads Using SIM_GPS Control
Table
Quad Timer Controlled
6-2. When GPIOC[3:0] are programmed to operate as peripheral I/O, then the
SPI Controlled
SIM_ GPS Register
56F8346 Technical Data, Rev. 15
GPIO Controlled
0
1
GPIOC_PER Register
0
1
I/O Pad Control
Register Descriptions
119

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