MC56F8346 Freescale Semiconductor, Inc, MC56F8346 Datasheet - Page 29

• Manufacturer Part Number: MC56F8346
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Preliminary
Signal Name
PHASEA0
(GPIOC4)
TRST
(TA0)
TDO
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Pin No.
124
120
139
Schmitt
Schmitt
Schmitt
Schmitt
Output
Output
Output
Input/
Input/
Type
Input
Input
pulled high
disabled,
pull-up is
internally
output is
In reset,
enabled
enabled
During
pull-up
56F8346 Technical Data, Rev. 15
Reset
Input,
Input,
State
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Test Reset — As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted whenever RESET is asserted. The
only exception occurs in a debugging environment when a
hardware device reset is required and the JTAG/EOnCE module
must not be reset. In this case, assert RESET, but do not assert
TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Note:
design is to be used in a debugging environment, TRST may be tied to
V
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is PHASEA0.
To deactivate the internal pull-up resistor, clear bit 4 of the
GPIOC_PUR register.
SS
through a 1K resistor.
For normal operation, connect TRST directly to V
Signal Description
SS
. If the
Signal Pins
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