MC56F8366 Freescale Semiconductor, Inc, MC56F8366 Datasheet - Page 179

• Manufacturer Part Number: MC56F8366
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

12.3 Power Distribution and I/O Ring Implementation
Figure 12-1
contains two internal power regulators. One of them is powered from the V
be turned off. This regulator controls power to the internal clock generation circuitry. The other regulator
is powered from the V
peripherals and the internal memories. This regulator can be turned off, if an external V
is externally applied to the V
In summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is
enabled. If the regulator is not enabled, a dual supply 3.3V/2.5V configuration can also be used.
Notes:
Freescale Semiconductor
Preliminary
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Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the V
Take special care to minimize noise levels on the V
Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. Designs that do not require debugging functionality, such as
consumer products, should tie these pins together.
Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an
interface to this port to allow in-circuit Flash programming
Flash, RAM and internal logic are powered from the core regulator output
V
All circuitry, analog and digital, shares a common V
PP
1 and V
V
DDA_OSC_PLL
illustrates the general power control incorporated in the 56F8366/56F8166. This chip
DD
REG
and V
PP
2 are not connected in the customer system
DD_IO
SS
circuits.
OSC
CAP
pins and provides power to all of the internal digital logic of the core, all
pins.
Figure 12-1 Power Management
REG
V
56F8366 Technical Data, Rev. 6
DD
CORE
V
SS
V
REF
SS
CAP
, V
bus
DDA
I/O
and V
Power Distribution and I/O Ring Implementation
SSA
pins
DDA_OSC_PLL
V
V
SSA_ADC
ADC
DDA_ADC
DD_CORE
V
V
V
V
V
pin and cannot
REFH
REFP
REFMID
REFN
REFLO
voltage
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