MC56F8366 Freescale Semiconductor, Inc, MC56F8366 Datasheet - Page 20

• Manufacturer Part Number: MC56F8366
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

20
Signal Name
(GPIOA10)
(GPIOA11)
(GPIOA12)
(GPIOA13)
(GPIOA8)
(GPIOA9)
CLKO
A0
A1
A2
A3
A4
A5
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Pin No.
138
10
11
12
13
14
3
Output
Output
Output
Input/
Type
disabled,
pull-up is
output is
output is
disabled
In reset,
In reset,
enabled
During
Reset
State
56F8366 Technical Data, Rev. 6
Clock Output — This pin outputs a buffered clock signal. Using
the SIM CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled, CLK_MSTR
(system clock), IPBus clock, oscillator output, prescaler clock and
postscaler clock. Other signals are also available for test purposes.
See
Address Bus — A0 - A5 specify six of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A0–A5 and EMI control signals are tri-stated when the
external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, set the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA8, set bit 8 in the GPIOA_PUR register.
Part 6.5.7
for details.
Signal Description
Freescale Semiconductor
Preliminary