OM6208 NXP Semiconductors, OM6208 Datasheet - Page 25

• Manufacturer Part Number: OM6208
• Description: Om6208 65 X 96 Pixels Matrix Grey-scale Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
11 INSTRUCTIONS
The OM6208 may be interfaced via 3-line or 4-line Serial
Peripheral Interface (SPI), 3-line serial interface or I
interface. In all cases, processing of instructions is
asynchronous and does not require the internal/external
oscillator to be running.
Data transmission to OM6208 may be of two types, those
that define the operating mode of the device (commands)
and those that fill display RAM (data). Table 7 lists all
commands that are recognised by OM6208.
The Most Significant Bit (MSB) is sent first. The mode in
which the D/C bit is defined varies with the type of serial
interface that is used.
Table 7 Instruction set
Instructions not expressly defined in this table and reserved instructions must not be used.
2003 feb 10
Write data
Horizontal addressing
Horizontal addressing
Power control
Charge pump control
Set V
Set V
Set bias
Display mode
Display mode
Display mode
Data order
RAM addressing
Vertical addressing
Vertical addressing
Vertical mirroring
ID read
ID read
ID read
ID read
Temperature sense
VM read
Row control
COMMAND NAME
65 x 96 pixels matrix grey-scale LCD driver
PR
PR
D/C
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(MSB)
D
0
0
0
0
0
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
(1)
7
D6
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
(1)
6
D5
D
0
0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
(1)
5
COMMAND BYTE
2
C-bus
V
D4
D
0
1
0
1
0
1
0
0
0
0
0
1
1
0
1
1
1
1
1
1
0
(1)
pr4
4
25
V
MY
D/C bit definitions:
Commands can consist of one byte (single-byte) and two
bytes (double-byte). Unless otherwise specified,
commands may be executed in any order.
D3
D
X
Y
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
(1)
(1)
pr3
3
3
3
With 4-line SPI interface selected, the D/C bit is
implemented as hard-wired input at pad D/C
With 3-line SPI interface selected, the D/C bit is not
implemented and all transmission are commands by
default unless preceded by the Display data length
command
With 3-line serial and I
bit is implemented through the interface protocol.
V
V
BS
PC
D2
D
X
X
Y
1
1
1
1
0
0
1
0
0
1
1
1
1
0
(1)
pr7
pr2
(1)
2
6
2
2
2
V
V
BS
D1
D
X
X
S
Y
0
0
1
1
0
1
1
1
1
0
0
1
1
0
(1)
pr6
pr1
(1)
1
1
5
1
1
1
(LSB)
DON
DOR
BRS
DAL
V
V
BS
D0
D
X
X
S
Y
Y
E
V
1
0
1
0
1
0
1
(1)
pr5
pr0
(1)
0
4
0
0
4
2
0
0
C-bus interface selected, the D/C
RAM data
set X address; lower 4 bits
set X address; upper 3 bits
charge pump on/off
set multiplication factor
write V
write V
set bias
all on/normal display
display ON/OFF
swap RAM MSB/LSB order
set Y address
set Y address
mirror Y
identification: ID1
identification: ID2
identification: ID3
identification: ID4
temperature read back
voltage monitor
swap the bottom rows
normal/inverse display
vertical or horizontal mode
FUNCTION DESCRIPTION
pr
pr
Product specification
register
register
OM6208
(3)(4)
(2)(3)
(2)(3)
(2)
(2)