OM6208 NXP Semiconductors, OM6208 Datasheet - Page 28

• Manufacturer Part Number: OM6208
• Description: Om6208 65 X 96 Pixels Matrix Grey-scale Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 9 Display and power mode bits DON, DAL and E
Notes
1. The DAL bit has priority over the E bit.
2. Refer also to Table 17.
3. X = don’t care.
Table 10 Multiplication settings for charge pump
11.2
Grey-scale mode and black-and-white mode require
different frame frequencies. The appropriate frame
frequency (f
(f
There are eight possible divider settings and these are
selected by the parameter FR[2:0], see Table 11.
2003 feb 10
osc
DON
65 x 96 pixels matrix grey-scale LCD driver
0
0
1
1
1
) using a presettable divider as shown in the equation
Frame frequency setting and oscillator tuning
S1
0
0
1
1
DAL
frame
0
1
0
0
1
(1)
) is derived from the oscillator frequency
f
frame
E
X
X
X
0
1
(2)
(3)
(3)
(3)
=
display off; all row and column
outputs at V
HV generator enabled
Power-down mode; display off;
all row and column outputs at
V
HV generator disabled
normal display mode
inverse display mode
all pixels on
-------------------------------- -
division ratio
S0
SS
0
1
0
1
; oscillator off;
f
OSC
DESCRIPTION
SS
; oscillator on;
MULTIPLIER
VOLTAGE
4
5
6
7
28
Table 11 Frame frequencies for f
Oscillator tuning is controlled by the parameter T[2:0]. As
a result of oscillator tuning, f
approximately 4% per step according to the equation
where T is the decimal value of T[2:0].
Example. For the default values given in Table 8
(i.e. FR[2:0] = 001 and T[2:0] = 110) the selected frame
frequency is 122.5 Hz
Equation (1) shows the typical value of the oscillator
frequency. The accuracy of this parameter is defined in
Chapter 15. The frame frequency accuracy results directly
from the oscillator accuracy.
11.3
Immediately following power-on, all internal registers and
the RAM content are undefined. A reset pulse must be
applied to the RES pad.
Reset is accomplished by applying an external reset pulse
(active LOW) to the RES input. When reset occurs within
the specified time, all internal registers are reset, however
the RAM remains undefined. The state after reset is
described in Section 11.4.
At power-on, the RES input must be 0.3V
reaches V
after V
pulse can be applied when V
A reset can also be made by sending a reset command.
This command can be used during normal operation but
not to initialize the chip after power-on.
After power-off, the RES input must not be HIGH when
V
DD1
FR2
0
0
0
0
1
1
1
1
is not HIGH.
DD1
Initialization
FR1
DD(min)
going HIGH (see Fig.37). Alternatively a reset
f
0
0
1
1
0
0
1
1
OSC
=
(or higher) within the maximum time t
FR0
400 kHz
0
1
0
1
0
1
0
1
(1 + 6
DIVISION
OSC
RATIO
DD1
11428
2448
3265
4082
4896
5714
7340
8968
1
is increased by
0.04) = 151.9 Hz.
+
is stable.
osc
0.04 T
= 400 kHz
Product specification
OM6208
DD1
f
frame
when V
163.4
122.5
98.0
81.7
70.0
54.5
44.6
35.0
(Hz)
VHRL
DD1
(1)