OM6208 NXP Semiconductors, OM6208 Datasheet - Page 7

• Manufacturer Part Number: OM6208
• Description: Om6208 65 X 96 Pixels Matrix Grey-scale Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7
7.1
One of four industrial standard interfaces can be selected
using the interface configuration inputs PS1 and PS0.
Table 1 Serial/I
7.2
The on-chip oscillator provides the clock signal for the
display system. No external components are required
when the internal oscillator is used. An external clock
signal, if used, is connected to this input.
7.3
The Address Counter (AC) assigns addresses to the
display data RAM for writing. The X address X[6:0] and the
Y address Y[4:0] are set separately.
7.4
The OM6208 contains a 65
stores the display data. The display data RAM is divided
into 17 banks of 96 bytes, although only two bits of the
17th bank are used. During RAM access, data is
transferred to the RAM via the serial interface. There is a
direct correspondence between X address and column
output number.
7.5
The display is generated by simultaneously reading out
the RAM content for two or four rows, depending on the
current display size that is selected. This content will be
processed with the corresponding set of two or four
orthogonal functions and so generate the signals for
switching the pixels of the display on or off according to the
RAM content.
The display status (all dots on/all dots off and
normal/inverse video) is set by the bits DON, DAL and E
in the command Display control (see Table 8).
2003 feb 10
65 x 96 pixels matrix grey-scale LCD driver
PS1
FUNCTIONAL DESCRIPTION
0
0
1
1
I/O buffers and interfaces
Oscillator
Address counter
Display data RAM
Display address counter
PS0
2
0
1
0
1
C-bus interface selection
3-line SPI
4-line SPI
I
3-line serial interface
2
C-bus interface
SELECTED INTERFACE
96
2 bit static RAM which
7
7.6
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not affected by operations on the data bus.
7.7
The data processing block receives data from the RAM
and the orthogonal function from the logic circuits, then
selects the correct voltage level to be provided to the
columns.
7.8
The high voltage generator provides the programmed
V
7.9
The bias voltage generator generates all the voltage levels
required for the MRA driving system.
7.10
The command decoder identifies command words arriving
at the interface and routes the data bytes that follow to
their destination.
7.11
The orthogonal function generator generates a set of
orthogonal functions suitable for the selected value of p
(number of active rows).
7.12
The reset block handles the hardware reset input (RES)
and software reset and provides all internal blocks with the
required reset signal.
7.13
The OM6208 contains 65 row and 96 column drivers
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. A typical MRA driving scheme with waveforms
for p = 4 is shown in Fig.2. The value of p represents the
number of simultaneously selected rows.
LCD
to the bias voltage generator block.
Timing generator
Data processing
High voltage generator
Bias voltage generator
Command decoder
Orthogonal function generator
Reset
Row drivers and column drivers
Product specification
OM6208