HFC-U Cologne Chip AG, HFC-U Datasheet - Page 10

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

2.4
2.5
(e. g. for PCM codecs)
March 1997
Pin No.
85
86
87
88
38
91
92
u)
GCI/IOM bus interface
internal pull up
Slot enable signals
C4IO
F0IO
GCI_OUT
GCI_IN
GCI_SYNC
F1_A
F1_B
Pin Name
Tristate
Output
I/OT
I/OT
Input
I/O
I/O
I
O
O
u)
u)
u)
u)
u)
all
all
all
all
all
all
all
Mode Function
double bit clock
GCI/IOM bus clock master output
GCI/IOM bus clock slave input (reset default)
Frame synchronisation, 8kHz pulse for GCI/IOM
bus frame synchronisation
GCI/IOM bus master output
GCI/IOM bus slave input (reset default)
GCI/IOM bus data II output
B1/B2 slot programmable as input or output
GCI/IOM bus data I input
B1/B2 slot programmable as input or output
synchronisation input for GCI in master mode
Must be feed with 8 kHz signal or left open.
enable signal for external CODEC A
Programmable as positive (reset default) or
negative pulse.
enable signal for external CODEC B or 2nd HFC-
U
Programmable as positive (reset default) or
negative pulse.
HFC-U
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