HFC-U Cologne Chip AG, HFC-U Datasheet - Page 2

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

Contents
1 General description ..........................................................................................................................................4
1.1 Applications .................................................................................................................................................... 5
1.2 Mode description ............................................................................................................................................. 5
2 Pin description ..................................................................................................................................................7
2.1 ISA-PC bus and microprocessor interface .......................................................................................................7
2.2 SRAM Interface .............................................................................................................................................. 8
2.3 Oscillator ......................................................................................................................................................... 9
2.4 GCI/IOM bus interface ..................................................................................................................................10
2.5 Slot enable signals .........................................................................................................................................10
2.6 Interrupt outputs ............................................................................................................................................ 11
2.7 Reset.............................................................................................................................................................. 11
2.8 Miscellaneous pins ........................................................................................................................................11
2.9 Power supply ................................................................................................................................................. 12
2.10 RESET characteristics .................................................................................................................................12
3 Functional description....................................................................................................................................13
3.1 ISA-PC mode ................................................................................................................................................ 13
3.2 Processor mode ............................................................................................................................................. 15
3.3 Register description .......................................................................................................................................16
3.4 Watchdog / timer ........................................................................................................................................... 18
3.5 FIFOs ............................................................................................................................................................ 19
3.6 External SRAM ............................................................................................................................................. 25
3.7 Busy synchronisation ....................................................................................................................................26
4 Register bit description ..................................................................................................................................28
4.1 Register bit description of GCI/IOM bus section .......................................................................................... 28
4.2 Register bit description of interrupt, status and control registers ...................................................................30
5 Electrical characteristics ................................................................................................................................35
6 Timing characteristics....................................................................................................................................37
6.1 ISA-PC bus or processor access .................................................................................................................... 37
6.2 SRAM access ................................................................................................................................................ 38
6.3 GCI/IOM timing ............................................................................................................................................ 39
7 GCI frame structure.......................................................................................................................................41
8 HFC-U package dimensions ..........................................................................................................................42
March 1997
1.2.1 ISA-PC mode ........................................................................................................................................... 5
1.2.2 Processor interface modes ........................................................................................................................ 6
3.1.1 Programming of I/O addresses ............................................................................................................... 13
3.1.2 ISA-PC bus interface ............................................................................................................................. 14
3.3.1 FIFO control registers ............................................................................................................................ 16
3.3.2 Registers of the GCI/IOM bus section ...................................................................................................17
3.3.3 Interrupt and status register .................................................................................................................... 18
3.5.1 FIFO channel operation ......................................................................................................................... 20
3.5.2 Transparent mode of HFC-U ................................................................................................................. 24
3.7.1 Busy synchronisation with status read ...................................................................................................26
3.7.2 Busy synchronisation with IOCHRDY ..................................................................................................27
3.5.1.1 Send channels (B1, B2 and D transmit) ......................................................................................... 20
3.5.1.2 FIFO full condition in send channels ............................................................................................. 21
3.5.1.3 Receive Channels (B1, B2 and D reiceive) .................................................................................... 21
3.5.1.4 FIFO full condition in receive channels ......................................................................................... 22
3.5.1.5 FIFO initialisation .......................................................................................................................... 23
HFC-U
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