HFC-U Cologne Chip AG, HFC-U Datasheet - Page 8

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

2.2
March 1997
Pin No.
Pin No.
15
16
17
18
21
22
23
24
25
26
27
28
31
32
53
54
55
56
57
58
59
60
63
64
1)
SRAM Interface
open drain, external pull up resistor required
/AEN
/CS
IOCHRDY
/IOR
/DS
/IOW
R/W
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BUSDIR
ALE
SRD0
SRD1
SRD2
SRD3
SRD4
SRD5
SRD6
SRD7
SRA0
SRA1
Pin Name
Pin Name
Tristate
Output
Tristate
Input
Output
OT
OT
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
O
O
1)
1)
1
2,3,4
1
2,3,4
1,3,4
2
1,3,4
2
all
all
all
all
all
all
all
all
all
Mode Function
SRAM data bus
SRAM data bit 0 (LSB)
SRAM data bit 1
SRAM data bit 2
SRAM data bit 3
SRAM data bit 4
SRAM data bit 5
SRAM data bit 6
SRAM data bit 7 (MSB)
SRAM address bus
SRAM address bus bit 0 (LSB)
SRAM address bus bit 1
Function
PC bus address enable
chipselect low active
I/O channel ready
low active wait signal for external processor
I/O read enable
I/O data strobe
I/O write enable
Read/Write select (WR='0')
Databus bit 0 (LSB)
Databus bit 1
Databus bit 2
Databus bit 3
Databus bit 4
Databus bit 5
Databus bit 6
Databus bit 7 (MSB)
Databus direction signal for external busdriver
'0'
Address latch enable
ALE to GND and IIOSEL0-3 0000: mode 1
ALE to VDD and IIOSEL0-3=0000:
ALE to GND and IIOSEL0-3=0000:
pulse on ALE and IIOSEL0-3=0000: mode 4
BD0-BD7 are outputs
mode 2
mode 3
HFC-U
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