HFC-U Cologne Chip AG, HFC-U Datasheet - Page 17

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

3.3.2 Registers of the
GCI/IOM bus timeslot selection registers
GCI/IOM bus data registers
March 1997
FIFO change
Changing the FIFO must be the last FIFO operation in a non BUSY phase. The new FIFO is
selected after one busy phase.
To select a new FIFO in processor mode a dummy value must be written to the Z1 register
address of this FIFO. The Z1 register is not changed by this operation.
Incrementation of the frame counters (F1, F2)
If the frame counters (F1, F2) are changed it must be in a seperate non BUSY period. That
means writing data to the FIFO or reading data from the FIFO is not allowed during this
period. Also selecting a new FIFO is not allowed. Reading the counters Z1, Z2, F1 and F2 is
allowed before incrementing the frame counter.
Accessability of registers
All operations on the FIFOs and on FIFO control registers and on B- and D-channel data
registers of the GCI/IOM bus part are only allowed in the non BUSY period of the HFC-U.
Status, interrupt and control registers can be read/written at any time.
CIP / I/O-address
00100000 20h
00100001 21h
00100010 22h
00100011 23h
CIP / I/O-address
00101000 28h
00101001 29h
00101010 2Ah
00101011 2Bh
00101100 2Ch
00101110 2Eh
important!
*)
These registers are read/written automatically by the HDLC FIFO controller (HFC).
Name
B1_SL
B2_SL
C/I
TRxR
Name
B1_D
B2_D
MON1_D
MON2_D
D_D
MST_MODE w
GCI/IOM
*)
*)
*)
bus section
r/w
w
w
r/w
r
r/w
r/w
r/w
r/w
r/w
w
Function
B1-slot mode register
B2-slot mode register
C/I command/indication register
Monitor Tx and Rx ready handshake
Function
B1 channel data register (slot #0 data)
B2 channel data register (slot #1 data)
first monitor byte (slot #2 data)
second monitor byte (slot #2 data)
mode register for GCI/IOM bus
HFC-U
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