HFC-U Cologne Chip AG, HFC-U Datasheet - Page 23

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

HFC-U
3.5.1.4 FIFO full condition in receive channels
Because the ISDN-B-channels and the ISDN-D-channels have no hardware based flow control there
is no possibility to stop input data if a receive FIFO is full.
So there is no FIFO full condition implemented in the HFC-U. The HFC-U assumes that the FIFOs
are so deep that the host processor hardware is able to avoid any overflow of the receive FIFOs.
Overflow conditions are again more than 31 input frames (15 frames for D-channel) or a real
overflow of the FIFO because of excessive data.
Because HDLC procedures only know a window size of 7 frames no more than 7 frames are send
without software intervention. Due to the great depth of the FIFOs of the HFC-U it is easy to poll the
HFC-U even in large time intervalls without having to fear a FIFO overflow condition.
However to avoid any undetected FIFO overflows the software driver should check the number of
frames in the FIFO which is F1-F2. An overflow exists if the number (F1-F2) is less than the number
in the last reading even if there was no reading of a frame in between.
After a detected FIFO overflow condition the HFC-U must be reset via the software or hardware
RESET!
3.5.1.5 FIFO initialisation
All counters Z1, Z2, F1 and F2 of all FIFOs are initialized to all 1s after a RESET.
Then the result is Z1 = Z2 = 1FFF
and F1 = F2 = 1F
for the B-channels
h
h
and Z1 = Z2 = 1FFh and F1 = F2 = 1Fh for the D-channel.
Please mask bit 4 of D-channel from counter F1, F2.
The same initialisation is done if the bit 3 in the CIRM register is set (soft reset).
March 1997
23 of 43