HFC-U Cologne Chip AG, HFC-U Datasheet - Page 30

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

4.2
March 1997
Name
CIRM
CTMT
Register bit description of interrupt, status and control registers
(18h)
(19h)
Bits
2..0
3
4
5
6
7
0
1
r/w
w
w
w
w
w
w
w
w
Function
select IRQ channel in PC mode
'000' IRQ disable (reset default)
'001' IRQ_A
'010' IRQ_B
'011' IRQ_C
'100' IRQ_D
'101' IRQ_E
'110' IRQ_F
'111' IRQ disable
soft reset, similar as hardware reset; the registers CIP,
CIRM and CTMT are not changed so selected I/O address
is kept in ISA-PC mode. The reset is active until the bit is
cleared.
'1'
'0'
select memory
'0'
'1'
D-channel idle mode
'0'
'1'
clock divider
'0'
'1'
This bit should only be changed during soft reset.
GCI/IOM test loop
'0'
'1'
HDLC/transparent mode for channel B1
'0'
'1'
HDLC/transparent mode for channel B2
'0'
'1'
activate reset
deactivate reset (reset default)
32k x 8 external RAM (reset default)
flags are send in D-channel if no data is send
(reset default)
continous ones are send in D-channel if no data is
send
normal clock mode (reset default)
master clock is divided by 2
normal operation
GCI input data is received from GCI output data
GCI output data is not changed
HDLC mode (reset default)
transparent mode
HDLC mode (reset default)
transparent mode
8k x 8 external RAM
HFC-U
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