nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 109

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
11.3.3
The OPMCON register is used to control special behavior in some of the operation modes:
11.3.4
There are four reset sources that initiate the same reset/ start-up sequence. These are:
The RSTREAS register stores the reason for the last reset, all cleared indicates that the last reset was from
the on-chip reset generator. A write operation to the register will clear all bits. Unless cleared after read (by
on-chip reset or by a write operation), RSTREAS will be cumulative. That is, a reset from the debugger fol-
lowed by a watchdog reset will set RSTREAS to 110.
Revision 1.1
Addr
Addr
0xAE
•
•
•
•
0xB1
Reset from the on chip reset generator
Reset from pin
Reset generated from the on chip watchdog function
Reset from on-chip hardware debugger
Bit
Bit
7:2
7:3
2:0
1
0
Operational mode control - OPMCON
Reset result – RSTREAS
R/W
R/W
R/W Retention latch control
R/W Watchdog reset enable
R
-
-
Reserved (always write ‘0’ to these bits)
0: Latch open – pass through
1: Latch locked
To keep some internal chip setup, such as pin directions/setup, you need to lock
a set of retention latches before entering DeepSleep and memory retention
power saving modes. After a wake up you must re-establish the register settings
before opening the retention latches.
0: If the on-chip watchdog functionality is enabled it will keep running as long the
operational mode Deep Sleep is not entered.
1: The on-chip watchdog functionality will enter its reset state when the opera-
tional mode Memory Retention and Register Retention is entered.
Not used
000: On-chip reset generator
001: RST pin
010: Watchdog
100: Reset from on-chip hardware debugger
Table 61. RSTREAS register
Table 60. OPMCON register
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Function
Function
Reset value: 0x00