nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 46

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
3.5.3
The data FIFOs store transmitted payloads (TX FIFO) or received payloads that are ready to be clocked
out (RX FIFO). The FIFOs are accessible in both PTX mode and PRX mode.
The following FIFOs are present in the RF Transceiver:
Both FIFOs have a controller and are accessible through the SPI by using dedicated SPI commands. A TX
FIFO in PRX can store payloads for ACK packets to three different PTX operations. If the TX FIFO con-
tains more than one payload to a pipe, payloads are handled using the first in - first out principle. The TX
FIFO in a PRX is blocked if all pending payloads are addressed to pipes where the link to the PTX is lost.
In this case, the MCU can flush the TX FIFO using the FLUSH_TX command.
The RX FIFO in PRX can contain payloads from up to three different PTX operations and a TX FIFO in
PTX can have up to three payloads stored.
You can write to the TX FIFO using these three commands; W_TX_PAYLOAD and
W_TX_PAYLOAD_NO_ACK in PTX mode and W_ACK_PAYLOAD in PRX mode. All three commands provide
access to the TX_PLD register.
The RX FIFO can be read by the command R_RX_PAYLOAD in PTX and PRX mode. This command pro-
vides access to the RX_PLD register.
The payload in TX FIFO in a PTX is not removed if the MAX_RT IRQ is asserted.
You can read if the TX and RX FIFO are full or empty in the FIFO_STATUS register. TX_REUSE (also avail-
able in the FIFO_STATUS register) is set by the SPI command REUSE_TX_PL, and is reset by the SPI
commands W_TX_PAYLOAD or FLUSH TX.
Revision 1.1
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Note: The 3 bit pipe information in the STATUS register is updated during the RFIRQ high to low
TX three level, 32 byte FIFO
RX three level, 32 byte FIFO
Data FIFO
transition. The pipe information is unreliable if the STATUS register is read during an RFIRQ
high to low transition.
Data
Data
Figure 28. FIFO (RX and TX) block diagram
RX FIFO Controller
TX FIFO Controller
RX FIFO
TX FIFO
32 byte
32 byte
32 byte
32 byte
32 byte
32 byte
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Control
Control
Data
Data
command
decoder
SPI