nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 98

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
9.4.1
The IEN0 register is responsible for global interrupt system enabling/disabling and also Timer 0, 1 and 2,
Port 0 and Serial Port individual interrupts enabling/disabling.
9.4.2
The IEN1 register is responsible for RF, SPI and Timer 2 interrupts.
2-Wire Master SPI and Slave SPI share the same interrupt line.
9.4.3
The 14 interrupt sources are grouped into six priority groups. For each of the groups, one of four priority
levels can be selected. They can be selected by setting appropriate values in IP0 and IP1 registers.
Revision 1.1
Address Bit
Address Bit
Address
0xA8
0xB8
0xA6
Interrupt Enable 0 Register – IEN0
Interrupt Enable 1 Register – IEN1
Interrupt Priority Registers – IP0, IP1
7 1: Enable interrupts. 0: all interrupts are disabled
6 Not used
5 1: Enable Timer2 (tf2/exf2) interrupt.
4 1: Enable Serial Port (ri0/ti0) interrupt.
3 1: Enable Timer1 overflow (tf1) interrupt
2 1: Enable Power failure (POFIRQ) interrupt
1 1: Enable Timer0 overflow (tf0) interrupt.
0 1: Enable Interrupt From Pin (IFP) interrupt.
7
6
5
4
3
2
1
0
Bit
7:6 not used
5
4
3
2
1
0
1: Enable Timer2 external reload (exf2) interrupt
Not used
1: Internal wakeup (TICK) interrupt enable
1: Miscellaneous (MISCIRQ) interrupt enable
1: Wakeup on pin (WUOPIRQ) interrupt enable
1: 2-Wire completed (WIRE2IRQ) interrupt, SPI master/slave completed
(MSDONE/SSDONE) interrupt enable
1: RF (RFIRQ) interrupt enable
1: RF SPI ready (RFRDY) interrupt enable
1: Enable Interrupt from pin 2 to IFP
1: Enable Interrupt from pin 1 to IFP
1: Enable Interrupt from pin 0 to IFP
1: Enable 2-Wire completed (WIRE2IRQ) interrupt
1: Enable Master SPI completed (MSDONE)interrupt
1: Enable Slave SPI completed (SSDONE) interrupt
Description
Table 49. INTEXP register
Table 47. IEN0 register
Table 48. IEN1 register
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Description
Description
Reset value 0x01