nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 158

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
Revision 1.1
Address
(Hex)
Name/Mnemonic
clockFrequency
masterSelect
clockStop
xStop
xStart
Bit
3:2
6
5
4
1
Reset
value
00
0
0
0
0
Type
158 of 191
R/W Slave only:
R/W Master only:
R/W Master only:
R/W Frequency on SCL.
R/W 1: Master mode selected.
1: SCL is kept ‘low’ by the slave between byte
transfers. This buys the MCU time to read RX data
or write TX data. In TX mode SCL is released t
after TX data has been written to W2DAT. t
1400 ns in Standard and Fast modes, while t
5·T
released immediately after the RX data is read
from W2DAT.
Note: Update this bit before any transmissions
begin.
0: The 2-Wire Slave does not alter the clock.
1: Transmit stop condition 1) in RX mode: After the
ongoing byte reception is completed; or 2) in TX
mode: After any pending TX data is transmitted.
Note: Do not attempt to clear a stop bit by writing
a 0 to it.
0: No stop condition to be sent.
Cleared when the stop condition is transmitted.
Slave only:
1: Disable interrupt when stop condition is
detected.
0: Enable interrupt when stop condition is
detected.
1: Transmit start (repeated start) condition after
any pending TX data or stop condition.
Note: Do not attempt to clear a start bit by writing
a 0 to it.
0: No start (repeated start) condition to be sent.
Cleared when the start (repeated start) condition
is transmitted.
Slave only:
1: Disable interrupt on address match.
0: Enable interrupt on address match.
00: Idle.
01: 100 KHz (Standard mode). Requires a system
clock frequency of at least 4 MHz.
10: 400 KHz (Fast mode). Requires a system
clock frequency of at least 8 MHz.
11: reserved.
0: Slave mode selected.
ckCPU
in High-speed mode. In RX mode SCL is
Description
REL
REL
REL
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