nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 144

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
The SPI Master is configured through SPIMCON0 and SPIMCON1 . It is enabled by setting SPIMCON0.0 to
‘1’. The SPI Master supports all four SPI modes, selected by SPIMCON0.2 and SPIMCON0.1 as described
in
can run on one of six predefined frequencies in the range of 1/2 to 1/64 of the MCU clock frequency, as
defined by SPIMCON0.6 down to SPIMCON0.4 .
SPIMDAT accesses both the TX (write) and the RX (read) FIFOs, which are two bytes deep. The FIFOs
are dynamic and can be refilled according to the state of the status flags: “FIFO ready” means that the
FIFO can accept data. “Data ready” means that the FIFO can provide data, minimum one byte.
Four different sources can generate interrupt, unless they are masked by their respective bits in
SPIMCON1 . SPIMSTAT reveals which sources are active.
Revision 1.1
Address
section
(Hex)
0xFE
0xFF
18.3.3. The bit wise data order per byte on MMISO/MMOSI is defined by SPIMCON0.3 . MSCK
Name/mnemonic
spiMasterStatus
maskIrqTxFifo-
spiMasterData
rxDataReady
txFifoReady
txFifoEmpty
SPIMSTAT
SPIMDAT
rxFifoFull
Ready
Bit
3:0
7:0
0
3
2
1
0
Reset
value
0x03
0x00
Table 86. SPI Master registers
1
0
0
1
1
144 of 191
Type
R/W 1: Disable interrupt when a location is available in
R/W SPI Master data register.
R
R
R
R
R
TX FIFO.
0: Enable interrupt when a location is available in
TX FIFO.
SPI Master status register.
Interrupt source.
1: RX FIFO full.
0: RX FIFO can accept more data from SPI.
Cleared when the cause is removed.
Interrupt source.
1: Data available in RX FIFO.
0: No data in RX FIFO.
Cleared when the cause is removed.
Interrupt source.
1: TX FIFO empty.
0: Data in TX FIFO.
Cleared when the cause is removed.
Interrupt source.
1: Location available in TX FIFO.
0: TX FIFO full.
Cleared when the cause is removed.
Accesses TX (write) and RX (read) FIFO buffers,
both two bytes deep.
Description