nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 146

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
The SPI slave is configured through SPISCON0 and SPISCON1 . It is enabled by setting SPISCON0.0 to
‘1’. The SPI Slave supports all four SPI modes, selected by SPISCON0.2 and SPISCON0.1 as described
in
are six possible interrupt sources in the SPI Slave. Any one of them can be masked.
When an interrupt occurs, SPISSTAT provides information on what the source was.
SPISDAT is used for data access in both directions. Prior to the first clock from the external master, the
MCU can write a byte to SPISDAT and that byte will be transferred to the master on SMISO while data is
being transferred from the external master to the slave on SMOSI .
18.3.3
The four different SPI modes are presented in
Revision 1.1
Address
SPI mode
section
(Hex)
0XBF
0xB7
0
1
2
3
18.3.3. The bit wise data order per byte on SMISO/SMOSI is defined by SPISCON0.3 . There
Name/mnemonic
SPI timing
rxDataReady
spiSlaveData
clockPolarity
Reserved
Reserved
Reserved
Reserved
SPISDAT
scsnLow
0
0
1
1
Bit
7:0
5:0
4
3
2
1
0
clockPhase
Reset
value
Table 87. SPI Slave registers
0x3F
0x00
0
1
0
1
0
0
0
0
0
Table 88. SPI modes
Table 88. SPI
146 of 191
Type
R/W SPI Slave data register.
R
R
R
R
R
R
Leading
Leading
Trailing
Trailing
Clock shift edge
Interrupt source.
1: Negative edge of SCSN detected.
0: Negative edge of SCSN not detected.
Cleared when read.
Interrupt source.
1: Data available in RX FIFO.
0: No data in RX FIFO.
Cleared when the cause is removed.
Accesses the RX (read) /TX (write) FIFO buffer.
modes,
Falling
Falling
Rising
Rising
Figure 60.
Description
and
Leading
Leading
Clock sample edge
Trailing
Trailing
Figure
61..
Falling
Falling
Rising
Rising