MT54V512H18E Micron Semiconductor Products, Inc., MT54V512H18E Datasheet - Page 7

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MT54V512H18E

Manufacturer Part Number
MT54V512H18E
Description
9Mb QDR SRAM, 2.5V Vdd, HSTL , 4-Word Burst,
Manufacturer
Micron Semiconductor Products, Inc.
Datasheet
NOTE:
512K x 18, 2.5V V
MT54V512H18E_16_A.fm - Rev 10/02
1. The address is concatenated with 2 additional internal LSBs to facilitate burst operation. The address order is always
2. State transitions: RD = (R# = LOW); WT = (W# = LOW).
3. Read and write state machines can be active simultaneously. Read and write cannot be simultaneously initiated.
4. State machine control timing sequence is controlled by K
fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3. Bus cycle is terminated at the end of this sequence (burst
count = 4).
Read takes precedence.
WRITE ADDRESS;
READ ADDRESS;
LOAD NEW
LOAD NEW
R_Count=0;
W_Count=0
R_Init=1
DD
, HSTL, QDRb4 SRAM
RD & R_Count=4
WT & W_Count=4
always
always
W_Count=W_Count+2
R_Count=R_Count+2
WRITE DOUBLE;
READ DOUBLE;
Bus Cycle State Diagram
0.16µm Process
R_Count=2
W_Count=2
Figure 4:
always
always
7
RD
WT & R_Init=0
/WT & W_Count=4
ADDRESS BY TWO 1
/RD & R_Count=4
ADDRESS BY TWO 1
INCREMENT WRITE
INCREMENT READ
2.5V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
R_Init=0
DD
, HSTL, QDRb4 SRAM
WRITE PORT NOP
READ PORT NOP
POWER-UP
R_Init=0
512K x 18
©2002, Micron Technology Inc.
provided
provided
voltage
voltage
Supply
Supply
ADVANCE
/RD
/WT

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