MT55L1MY18F Micron Semiconductor Products, Inc., MT55L1MY18F Datasheet - Page 18

• Manufacturer Part Number: MT55L1MY18F
• Description: 18Mb ZBT SRAM, 3.3V Vdd, 2.5V or 3.3V I/O; 2.5V Vdd, 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

Notes
18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM
MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03
6. I
7. “Device deselected” means device is in power-
8. Typical values are measured at 3.3V, 25
1. All voltages referenced to V
2. For 3.3V V
3. For 2.5V V
4. The MODE and ZZ pins/balls have internal pull-
5. V
Overshoot: V
Undershoot:V
Power-up:
Overshoot: V
Undershoot:V
Power-up:
up/pull-down and input leakage = ±10µA.
can be externally wired together to the same
power supply.
increases with faster cycle times. I
with faster cycle times and greater output loading.
down mode as defined in the truth table. “Device
selected” means device is active (not in power-
down mode).
12ns cycle time.
DD
DD
I £ 20mA
I £ 20mA
t £ 200ms
I £ 20mA
I £ 20mA
t £ 200ms
Q should never exceed V
is specified with no output current and
DD
DD
V
:
V
:
IH
IL
IH
IL
IH
IH
³ -0.7V for t £
³ -0.5V for t £
£ +4.6V for t £
£ +3.6V for t £
£ +2.65V and V
£ +3.6V and V
SS
(GND).
t
t
DD
DD
KHKH/2 for
KHKH/2 for
t
t
KHKH/2 for
KHKH/2 for
DD
. V
£ 3.135V for
£ 2.375V for
DD
DD
Q increases
and V
º
C, and
DD
Q
18
18Mb: 1 MEG x 18, 512K x 32/36
10. This parameter is sampled.
11. OE# can be considered a “Don’t Care” during
12. Test conditions as specified with the output load-
13. A WRITE cycle is defined by R/W# LOW, having
14. Measured as HIGH above V
15. Refer to Technical Note TN-55-01, “Designing
16. This parameter is measure with the output load-
17. This is a synchronous device. All addresses must
9. Typical values are measured at 2.5V, 25
12ns cycle time.
WRITEs; however, controlling OE# can help fine-
tune a system for turnaround timing.
ing shown in Figures 11 and 12 for 3.3V I/O and
Figures 13 and 14 for 2.5V I/O unless otherwise
noted.
been registered into the device at ADV/LD# LOW.
A READ cycle is defined by R/W# HIGH with ADV/
LD# LOW. Both cases must meet setup and hold
times.
with ZBT SRAMs,” for a more thorough discussion
of these parameters.
ing shown in Figure 12 for 3.3V I/O and Figure 14
for 2.5V I/O.
meet the specified setup and hold times with sta-
ble logic levels for all rising edges of CLK when the
chip is enabled. To remain enabled, chip enable
must be valid at each rising edge of CLK when
ADV/LD# is LOW.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
FLOW-THROUGH ZBT SRAM
IH
and LOW below V
©2003 Micron Technology, Inc.
º
C, and
IL
.