MT55L256L32F Micron Semiconductor Products, Inc., MT55L256L32F Datasheet - Page 7

• Manufacturer Part Number: MT55L256L32F
• Description: 8Mb ZBT SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

TQFP PIN DESCRIPTIONS (CONTINUED)
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
MT55L512L18F_C.p65 – Rev. 2/02
(a)
15, 16, 41, 65, 91
66, 67, 71, 76, 90
5, 10, 14, 17, 21,
28-30, 51-53, 56,
(b)
54, 61, 70, 77
26, 40, 55, 60,
57, 75, 78, 79,
38, 39, 42, 43
68, 69, 72-74
18, 19, 22-24
4, 11, 20, 27,
1-3, 6, 7, 25,
58, 59, 62, 63,
8, 9, 12, 13,
95, 96
x18
n/a
88
31
84
15, 16, 41, 65, 91
66, 67, 71, 76, 90
(a)
(b)
(d)
5, 10, 14, 17, 21,
26, 40, 55, 60,
54, 61, 70, 77
38, 39, 42, 43
4, 11, 20, 27,
(c)
52, 53, 56-59,
68, 69, 72-75,
18, 19, 22-25,
x32/x36
62, 63
78, 79
12, 13
28, 29
2, 3, 6-9,
n/a
51
80
30
88
31
84
1
SYMBOL TYPE
NF/DQPa
NF/DQPb
NF/DQPd
NF/DQPc
MODE
(LBO#)
R/W#
V
DNU
DQa
DQb
DQd
DQc
V
V
NC
NF
DD
DD
SS
Q
Output “ b” is associated with DQb pins; Byte “ c” is associated
Supply
Supply
Supply
Input/
Input
Input
NF/
I/O
–
–
–
7
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted into
WRITEs (and vice versa) other than by loading a new
address. A LOW on this pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising
edge of CLK. Full bus-width WRITEs occur if all byte write
enables are LOW.
Mode: This input selects the burst sequence. A LOW on
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
SRAM Data I/Os: Byte “ a” is associated with DQa pins; Byte
with DQc pins; Byte “ d” is associated with DQd pins.
Input data must meet setup and hold times around the
rising edge CLK.
No Function/Data Bits: On the x32 version, these pins are
No Function (NC) and can be left floating or connected to
GND to minimize thermal impedance. On the x36 version,
these bits are DQs.
Power Supply: See DC Electrical Characteristics and
Operating Conditions for range.
Isolated Output Buffer Supply: See DC Electrical
Characteristics and Operating Conditions for range.
Ground: GND.
No Connect: These pins can be left floating or connected
to GND to minimize thermal impedance.
Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
No Function: This pin is internally connected to the die and
will have the capacitance of an input pin. It is allowable to
leave this pin unconnected or driven by signals. Pin 84 is
reserved as an address pin for the 18Mb ZBT SRAM.
Read/Write: This input determines the cycle type when
this pin selects linear burst. NC or HIGH on this pin selects
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.