MT55L256L32F Micron Semiconductor Products, Inc., MT55L256L32F Datasheet - Page 9

• Manufacturer Part Number: MT55L256L32F
• Description: 8Mb ZBT SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

FBGA PIN DESCRIPTIONS
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
MT55L512L18F_C.p65 – Rev. 2/02
8P, 8R, 9P, 9R,
3P, 3R, 4P, 4R, 3P, 3R, 4P, 4R,
10A, 10B, 10P, 9R, 10A, 10B,
10R, 11A, 11R 10P, 10R, 11R
2A, 9A, 2B,
x18
11H
4A
7A
3A
6A
6R
6P
5B
7B
6B
3B
8B
–
–
2A, 9A, 2B,
8P, 8R, 9P,
x32/x36
11H
5A
4A
7A
3A
6A
6R
6P
5B
4B
7B
6B
3B
8B
SYMBOL
OE#(G#)
BWb#
BWd#
BWa#
BWc#
CKE#
R/W#
CE2#
SA0
SA1
CLK
CE#
CE2
S A
ZZ
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(continued on next page)
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa; BWb#
controls DQb’s and DQPb; BWc# controls DQc’s and DQPc; BWd#
controls DQd’s and DQPd. Parity is only available on the x18 and x36
versions.
Synchronous Clock Enable: This active LOW input permits CLK to
propogate throughout the device. When CKE# is HIGH, the device
ignores the CLK input and effectively internally extends the
previous CLK cycle. This input must meet the setup and hold times
around the rising edge of CLK.
Read/Write: This input determines the cycle type when ADV/LD# is
LOW and is the only means for determining READs and WRITEs.
READ cycles may not be converted into WRITEs (and vice versa)
other than by loading a new address. A LOW on this pin permits
BYTE WRITE operations to meet the setup and hold times around
the rising edge of CLK. Full bus-width WRITEs occur if all byte write
enables are LOW.
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device. CE# is sampled only when a new external address is
loaded. (ADV/LD# is LOW)
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
9
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.