MT57W1MH18B Micron Semiconductor Products, Inc., MT57W1MH18B Datasheet

MT57W1MH18B

Manufacturer Part Number

MT57W1MH18B

Description

18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,

Manufacturer

Micron Semiconductor Products, Inc.

Datasheet

1.MT57W1MH18B.pdf (27 pages)

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18Mb DDRII CIO SRAM

2-Word Burst

Features

• DLL circuitry for accurate output data placement

• Pipelined, double-data rate operation

• Common data input/output bus

• Fast clock to valid data times

• Full data coherency, providing most current data

• Two-tick burst counter for low DDR transaction size

• Two input clocks (K and K#) for precise DDR timing at

• Two output clocks (C and C#) for precise flight time

• Optional-use echo clocks (CQ and CQ#) for flexible

• Permits up to one new data request per clock cycle

• Simple control logic for easy depth expansion

• Internally self-timed, registered writes

• Core V

• Clock-stop capability with µs restart

• 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA package

• User-programmable impedance output

• JTAG boundary scan

NOTE

18Mb: 1.8V V

MT57W1MH18B_H.fm – Rev. H, Pub. 3/03

Options

• Clock Cycle Timing

• Configurations

• Package

• Operating Temperature Range

1. A Part Marking Guide for the FBGA devices can be found on

clock rising edges only

and clock skew matching—clock and data delivered

together to receiving device

receive data synchronization

(±0.1V) HSTL

Micron’s Web

3ns (333 MHz)

3.3ns (300 MHz)

4ns (250 MHz)

5ns (200 MHz)

6ns (167 MHz)

7.5ns (133 MHz)

2 Meg x 8

1 Meg x 18

165-ball, 13mm x 15mm FBGA

Commercial (0°C £ T

512K x 36

, HSTL, DDRIIb2 SRAM

= 1.8V (±0.1V); I/O V

site—http://www.micron.com/numberguide.

£ +70°C)

Q = 1.5V to V

MT57W512H36B

MT57W1MH18B

MT57W2MH8B

Marking

None

-7.5

-3.3

-3

-4

-5

-6

2 MEG

Table 1:

General Description

SRAM employs high-speed, low-power CMOS designs

using an advanced 6T CMOS process.

advanced synchronous peripheral circuitry and a burst

counter. All synchronous inputs pass through registers

controlled by an input clock pair (K and K#) and are

latched on the rising edge of K and K#. The synchro-

nous inputs include all addresses, all data inputs,

active LOW load (LD#), read/write (R/W#), and active

LOW byte writes or nibble writes (BWx# or NWx#).

Write data is registered on the rising edges of both K

and K#. Read data is driven on the rising edge of C and

C# if provided, or on the rising edge of K and K# if C

and C# are not provided.

(ZQ). Synchronous data outputs (Q, sharing the same

physical balls as the data inputs D) are tightly matched

MT57W2MH8B

MT57W1MH18B

MT57W512H36B

PART NUMBER

MT57W2MH8BF-xx

MT57W1MH18BF-xx

MT57W512H36BF-xx

The Micron

The DDR SRAM integrates an SRAM core with

Asynchronous inputs include impedance match

1.8V V

Figure 1: 165-Ball FBGA

8, 1 MEG

Valid Part Numbers

DDRII synchronous, pipelined burst

, HSTL, DDRIIb2 SRAM

DESCRIPTION

2 Meg x 8, DDRIIb2 FBGA

1 Meg x 18, DDRIIb2 FBGA

512K x 36, DDRIIb2 FBGA

18, 512K

Related parts for MT57W1MH18B

MT57W1MH18B Summary of contents

Page 1

... Commercial (0°C £ T £ +70°C) A NOTE : 1. A Part Marking Guide for the FBGA devices can be found on Micron’s Web site—http://www.micron.com/numberguide. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG MT57W2MH8B MT57W1MH18B MT57W512H36B Table 1: PART NUMBER MT57W2MH8BF-xx MT57W1MH18BF-xx ...

Page 2

... NOP cycles are not required when switching from a WRITE to a READ. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. READ occurs after a WRITE cycle, address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without con- flicting with the read ...

Page 3

... The user can operate the part with fewer than 1,024 clock cycles, but optimal output impedance is not guaranteed. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Clock Considerations This device utilizes internal delay-locked loops for maximum output, data valid window. It can be placed into a stopped-clock state to minimize power with a modest restart time of 1,024 clock cycles ...

Page 4

... For 2 Meg 21 NWx separate nibble writes. For 1 Meg 18; BWx separate byte writes. For 512K 36; BWx separate byte writes. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 2: Functional Block Diagram 2 Meg Meg x 18; 512K x 36 n-1 ...

Page 5

... For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 3: Application Example R = 250Ω ...

Page 6

... Expansion address: 10A for 36Mb 5. Expansion address: 5B for 288Mb 6. NW0# controls writes to DQ0:DQ3 Note that the x8 does not permit random start address on the least-significant address bit; SA0 = 0 at the start of each access. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. R/W# ...

Page 7

... TCK SA NOTE : 1. Expansion address: 2A for 72Mb 2. BW1# controls writes to DQ9:DQ17 3. Expansion address: 7A for 144Mb 4. Expansion address: 10A for 36Mb 5. Expansion address: 5B for 288Mb 6. BW0# controls writes to DQ0:DQ8 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. R/W# K# BW1 ...

Page 8

... Expansion address: 2A for 144Mb 2. Expansion address: 3A for 36Mb 3. BW2# controls writes to DQ18:DQ26 4. BW1# controls writes to DQ9:DQ17 5. Expansion address: 10A for 72Mb 6. BW3# controls writes to DQ27:DQ35 7. BW0# controls writes to DQ0:DQ8 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. R/W# K# ...

Page 9

... Power Supply: GND. NC – No Connect: These balls are internally connected to the die, but have no function and may be left not connected to the board to minimize ball count. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG HSTL, DDRIIb2 SRAM DD if the JTAG function is not used ...

Page 10

... SA0 is internally advanced in accordance with the burst order table. Bus cycle is terminated after burst count = 2. 2. State transitions (LD# = LOW (LD# = HIGH (R/W# = HIGH (R/W# = LOW). 3. State machine, control timing sequence is controlled by K. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 4: Bus Cycle State Diagram L ...

Page 11

... This table illustrates operation for x18 devices. The x36 device operation is similar, except for the addition of BW2# (controls DQ18:DQ26) and BW3# (controls DQ27:DQ35). The x8 device operation is similar, except that NW0# con- trols DQ0:DQ3, and NW1# controls DQ4:DQ7. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. ...

Page 12

... Notes appear following parameter tables on page 16; 0°C £ T DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to ..... -0.5V to +2.8V SS the device ...

Page 13

... Input, Output Capacitance (DQ) Clock Capacitance Table 13: Thermal Resistance Note 13; notes appear following parameter tables on page 16 DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Balls (Bottom) 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V £ +70° SYMBOL TYP -3 ³ ...

Page 14

... KC 30 reset reset Output Times C, C# HIGH to t CHQV 0.45 output valid C, C# HIGH to t CHQX -0.45 output hold C, C# HIGH to t echo clock CHCQV 0.45 valid C, C# HIGH to t echo clock CHCQX -0.45 hold 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. 3.30 4.20 4.00 5.25 5.00 0.20 0.20 1.32 1.60 2.00 1.32 1.60 2.00 1.49 1.80 2.20 1.49 1.80 2.20 0.00 1.45 0.00 1.80 ...

Page 15

... IVKH 0.40 rising edge Data-in valid rising DVKH 0.28 edge Hold Times K rising edge t to address KHAX 0.40 hold K rising edge t to control KHIX 0.40 inputs hold K, K# rising t edge to data- KHDX 0.28 in hold 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. 0.27 0.30 0.35 -0.27 -0.30 -0.35 0.45 0.45 0.45 -0.45 -0.45 -0.45 0.40 0.50 0.60 0.40 0.50 0.60 0.30 0.35 0.40 0.40 0.50 0.60 0.40 ...

Page 16

... Typical values are measured at V 1.5V, and temperature = 25°C. 11. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are com- pleted. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. 12. Average I/O current and power is provided for OH informational purposes only and is not tested ...

Page 17

... Input rise and fall times . . . . . . . . . . . . . . . . . . . . 0.7ns Input timing reference levels . . . . . . . . . . . . . . . . 0.75V Output reference levels . . . . . . . . . . . . . . . . . . . . . V ZQ for 50 W impedance . . . . . . . . . . . . . . . . . . . . . 250 W Output load . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 5 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. HSTL, DDRIIb2 SRAM DD Output Load Equivalent V ...

Page 18

... Outputs are disabled (High-Z) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 6: READ/WRITE Timing NOP ...

Page 19

... The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK ...

Page 20

... TDI and TDO balls. This allows data to be shifted through the SRAM with mini- mal delay. The bypass register is set LOW (Vss) when the BYPASS instruction is executed. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. HSTL, DDRIIb2 SRAM DD ...

Page 21

... The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller Shift-DR state. It also places all SRAM outputs into a High-Z state. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG HSTL, DDRIIb2 SRAM DD SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149 ...

Page 22

... CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 10. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 9: TAP Timing (TCK) t THTL t t THTH ...

Page 23

... This table defines DC values for TAP control and data balls only. The DQ SRAM balls used in JTAG operation will have the DC values as defined in Table 9, “DC Electrical Characteristics and Operating Conditions,” on page 12. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. 1.8V TAP AC Output Load Equivalent ...

Page 24

... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V ALL DEVICES DESCRIPTION 000 Revision number. 00def0wx0t0q0b0s0 ...

Page 25

... V , HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. HSTL, DDRIIb2 SRAM DD BIT# FBGA BALL 37 10D 10C 40 11D 11B 44 11C 10B ...

Page 26

... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of of Micron Technology, Inc. 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 11: 165-Ball FBGA 0.12 C ...

Page 27

... Rev. 3, Pub. 12/01, ADVANCE .......................................................................................................................................12/01 • Changed AC Timing Rev. 2, Pub. 11/01, ADVANCE .......................................................................................................................................11/01 • New ADVANCE data sheet 18Mb: 1. HSTL, DDRIIb2 SRAM DD MT57W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG X 1.8V V test conditions for read to write ratio DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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