MT57W1MH18B Micron Semiconductor Products, Inc., MT57W1MH18B Datasheet - Page 10
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MT57W1MH18B
Manufacturer Part Number
MT57W1MH18B
Description
18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,
Manufacturer
Micron Semiconductor Products, Inc.
Datasheet
1.MT57W1MH18B.pdf
(27 pages)
Table 6:
x18, x36 only
NOTE
18Mb: 1.8V V
MT57W1MH18B_H.fm – Rev. H, Pub. 3/03
1. SA0 is internally advanced in accordance with the burst order table. Bus cycle is terminated after burst count = 2.
2. State transitions: L = (LD# = LOW); L# = (LD# = HIGH); R = (R/W# = HIGH); W = (R/W# = LOW).
3. State machine, control timing sequence is controlled by K.
LOAD NEW ADDRESS
:
DD
, HSTL, DDRIIb2 SRAM
Count = 0
FIRST ADDRESS (EXTERNAL)
Burst Address Table
X . . . X0
X . . . X1
L, Count = 2
R
W
L, Count = 2
Bus Cycle State Diagram
Count = Count + 2
Count = Count + 2
WRITE DOUBLE
READ DOUBLE
Figure 4:
L
10
2 MEG
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
L#, Count = 2
X
SECOND ADDRESS (INTERNAL)
L#, Count = 2
8, 1 MEG
DD
, HSTL, DDRIIb2 SRAM
X . . . X1
X . . . X0
X
POWER-UP
18, 512K
NOP
provided
voltage
Supply
©2003 Micron Technology, Inc.
X
36
L#