MT58L128L32P1 Micron Semiconductor Products, Inc., MT58L128L32P1 Datasheet - Page 10

• Manufacturer Part Number: MT58L128L32P1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

FBGA PIN DESCRIPTIONS (continued)
10L, 10M, 11D, 10L, 10M, 11J,
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
1H, 4D, 4E, 4F, 1H, 4D, 4E, 4F,
11E, 11F, 11G 11K, 11L, 11M
(a)
1L, 1M, 2D,
4K, 4L, 4M,
3K, 3L, 3M,
3N, 9C, 9D,
8K, 8L, 8M
3C, 3D, 3E,
4G, 4H, 4J,
8D, 8E, 8F,
8G, 8H, 8J,
9E, 9F, 9G,
2E, 2F, 2G
3F, 3G, 3J,
(b)
9J, 9K, 9L,
9M, 9N
10J, 10K,
x18
11C
8A
1J, 1K,
1N
9B
1R
–
–
10F, 10G, 11D,
11E, 11F, 11G
(b)
(d)
(a)
1F, 1G, 2D,
4K, 4L, 4M,
3K, 3L, 3M,
3N, 9C, 9D,
1M, 2J, 2K,
8K, 8L, 8M
3C, 3D, 3E,
4G, 4H, 4J,
8D, 8E, 8F,
8G, 8H, 8J,
9E, 9F, 9G,
2E, 2F, 2G
3F, 3G, 3J,
9J, 9K, 9L,
x32/x36
(c)
9M, 9N
2L, 2M
1J, 1K, 1L,
10D, 10E,
10J, 10K,
11N
11C
1D, 1E,
8A
1N
9B
1R
1C
SYMBOL
NC/DQPb
NC/DQPd
NC/DQPa
NC/DQPc
ADSP#
ADSC#
MODE
(LB0#)
V
DQb
DQd
DQa
DQc
V
DD
DD
Q
Output Byte “b” is associated with DQbs. For the x32 and x36 versions,
Supply Power Supply: See DC Electrical Characteristics and Operating
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas;
TYPE
Input Synchronous Address Status Processor: This active LOW input
Input Synchronous Address Status Controller: This active LOW input
Input Mode: This input selects the burst sequence. A LOW on this input
NC/
I/O
(continued on next page)
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
selects “linear burst.” NC or HIGH on this input selects “interleaved
burst.” Do not alter input state while device is operating.
Byte “a” is associated with DQas; Byte “b” is associated with
DQbs; Byte “c” is associated with DQcs; Byte “d” is associated
with DQds. Input data must meet setup and hold times around
the rising edge of CLK.
No Connect/Parity Data I/Os: On the x32 version, these are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa;
Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is
DQPd.
Conditions for range.
and Operating Conditions for range.
10
PIPELINED, SCD SYNCBURST SRAM
4Mb: 256K x 18, 128K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2003, Micron Technology, Inc.