MT58L128L32P1 Micron Semiconductor Products, Inc., MT58L128L32P1 Datasheet - Page 24

• Manufacturer Part Number: MT58L128L32P1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
BWa#-BWd#
ADDRESS
(NOTE 2)
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or GW#
BWE#,
ADSP#
ADSC#
ADV#
GW#
OE#
CLK
CE#
is HIGH, CE2# is HIGH and CE2 is LOW.
data contention for the time period prior to the byte write enable inputs being sampled.
HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
D
Q
BURST READ
High-Z
t ADSS
t CES
t AS
(WRITE timing parameters are contained on the following page.)
A1
t ADSH
t CEH
t AH
t KH
t OEHZ
(NOTE 3)
Byte write signals are
ignored for first cycle when
ADSP# initiates burst.
t KC
t ADSS
t KL
Single WRITE
t DS
D(A1)
t ADSH
t DH
A2
(NOTE 4)
D(A2)
WRITE TIMING
D(A2 + 1)
(NOTE 1)
t WS
BURST WRITE
24
t WH
PIPELINED, SCD SYNCBURST SRAM
(NOTE 5)
D(A2 + 1)
4Mb: 256K x 18, 128K x 32/36
ADV# suspends burst.
D(A2 + 2)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ADSC# extends burst.
D(A2 + 3)
t ADSS
A3
D(A3)
t ADSH
DON’T CARE
Extended BURST WRITE
t WS
t AAS
D(A3 + 1)
t AAH
t WH
©2003, Micron Technology, Inc.
UNDEFINED
D(A3 + 2)