MT58L128L32P1 Micron Semiconductor Products, Inc., MT58L128L32P1 Datasheet - Page 22

• Manufacturer Part Number: MT58L128L32P1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

GW#, BWE#,
BWa#-BWd#
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
ADDRESS
(NOTE 2)
ADSP#
ADSC#
ADV#
OE#
CLK
CE#
Q
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to
4. Outputs are disabled within one clock cycle after deselect.
is HIGH, CE2# is HIGH and CE2 is LOW.
be driven until after the following clock rising edge.
t ADSS
t AS
t CES
A1
t ADSH
t AH
t CEH
t KH
(NOTE 3)
High-Z
t KC
(READ timing parameters are contained on the following page.)
t WS
t KL
Single READ
t KQLZ
t WH
t KQ
t ADSS
A2
Q(A1)
t ADSH
t OEHZ
t AAS
t AAH
t OELZ
t OEQ
READ TIMING
(NOTE 1)
Q(A2)
t KQX
t KQ
22
Q(A2 + 1)
PIPELINED, SCD SYNCBURST SRAM
ADV#
suspends
burst.
4Mb: 256K x 18, 128K x 32/36
3
Q(A2 + 2)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BURST READ
Q(A2 + 3)
A3
Q(A2)
Burst continued with
new base address.
Burst wraps around
to its initial state.
DON’T CARE
Q(A2 + 1)
©2003, Micron Technology, Inc.
t KQHZ
Deselect
cycle.
(NOTE 4)
UNDEFINED