MT58L128L32P1 Micron Semiconductor Products, Inc., MT58L128L32P1 Datasheet - Page 26

• Manufacturer Part Number: MT58L128L32P1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

BWa#-BWd#
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
ADDRESS
(NOTE 4)
(NOTE 2)
ADSP#
ADSC#
BWE#,
ADV#
OE#
CLK
CE#
Q
D
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
6. Timing is shown assuming that the device was not enabled before entering into this sequence.
is HIGH, CE2# is HIGH and CE2 is LOW.
A1
High-Z
High-Z
t ADSS
t CES
t AS
A2
(READ/WRITE timing parameters are contained on the following page.)
Back-to-Back READs
t ADSH
t CEH
t KH
t AH
t KC
t KQLZ
(NOTE 5)
Q(A1)
t KL
t KQ
Q(A2)
t OEHZ
t WS
Single WRITE
t DS
D(A3)
READ/WRITE TIMING
A3
t DH
t WH
A4
26
t OELZ
PIPELINED, SCD SYNCBURST SRAM
4Mb: 256K x 18, 128K x 32/36
(NOTE 1)
Q(A4)
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BURST READ
Q(A4+1)
Q(A4+2)
Q(A4+3)
DON’T CARE
©2003, Micron Technology, Inc.
D(A5)
A5
Back-to-Back
WRITEs
UNDEFINED
D(A6)
A6