EPCS64 Altera Corporation, EPCS64 Datasheet - Page 12

• Manufacturer Part Number: EPCS64
• Description: (EPCS1 - EPCS64) Serial Configuration Devices
• Manufacturer: Altera Corporation

Serial Configuration Device Memory Access
4–12
Configuration Handbook, Volume 2
Figure 4–5. Write Enable Operation Timing Diagram
Write Disable Operation
The write disable operation code is b'0000 0100, with the MSB listed
first. The write disable operation resets the write enable latch bit, which
is bit 1 in the status register. To prevent the memory from being written
unintentionally, the write enable latch bit is automatically reset when
implementing the write disable operation as well as under the following
conditions:
■
■
■
■
■
Figure 4–6
Figure 4–6. Write Disable Operation Timing Diagram
DCLK
DCLK
DATA
DATA
ASDI
ASDI
nCS
nCS
Power up
Write bytes operation completion
Write status operation completion
Erase bulk operation completion
Erase sector operation completion
Core Version a.b.c variable
shows the timing diagram for the write disable operation.
High Impedance
High Impedance
0
0
1
1
2
2
Operation Code
Operation Code
3
3
4
4
5
5
6
6
Altera Corporation
7
7
July 2004