EPCS64 Altera Corporation, EPCS64 Datasheet - Page 15

• Manufacturer Part Number: EPCS64
• Description: (EPCS1 - EPCS64) Serial Configuration Devices
• Manufacturer: Altera Corporation

Figure 4–9. Read Status Operation Timing Diagram
Altera Corporation
July 2004
DCLK
ASDI
DATA
nCS
0
High Impedance
1
2
Operation Code
3
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Write Status Operation
The write status operation code is b'0000 0001, with the MSB listed
first. Use the write status operation to set the status register block
protection bits. The write status operation has no effect on the other bits.
Therefore, designers can implement this operation to protect certain
memory sectors, as defined in
protect bits, the protected memory sectors are treated as read-only
memory. Designers must execute the write enable operation before the
write status operation so the device sets the status register’s write enable
latch bit to 1.
The write status operation is implemented by driving nCS low, followed
by shifting in the write status operation code and one data byte for the
status register on the ASDI pin.
the write status operation. nCS must be driven high after the eighth bit of
the data byte has been latched in, otherwise, the write status operation is
not executed.
Immediately after nCS is driven high, the device initiates the self-timed
write status cycle. The self-timed write status cycle usually takes 5 ms for
both serial configuration devices and is guaranteed to be less than 15 ms
(see t
that the status register is written with desired block protect bits.
Alternatively, you can check the write in progress bit in the status register
by executing the read status operation while the self-timed write status
cycle is in progress. The write in progress bit is 1 during the self-timed
write status cycle, and is 0 when it is complete.
4
5
WS
6
in
Core Version a.b.c variable
7
Table
MSB
7
8
6
4–12). Designers must account for this delay to ensure
9
Status Register Out
5
10
4
11
3
12
Tables 4–9
2
13
Figure 4–10
1
14
0
15
MSB
Configuration Handbook, Volume 2
7
and 4–10. After setting the block
shows the timing diagram for
6
5
Status Register Out
4
3
2
1
0
7
4–15