EPCS64 Altera Corporation, EPCS64 Datasheet - Page 16

• Manufacturer Part Number: EPCS64
• Description: (EPCS1 - EPCS64) Serial Configuration Devices
• Manufacturer: Altera Corporation

Serial Configuration Device Memory Access
Figure 4–10. Write Status Operation Timing Diagram
4–16
Configuration Handbook, Volume 2
DCLK
ASDI
DATA
nCS
0
High Impedance
1
Read Bytes Operation
The read bytes operation code is b'0000 0011, with the MSB listed first.
To read the memory contents of the serial configuration device, the
device is first selected by driving nCS low. Then, the read bytes operation
code is shifted-in followed by a 3-byte address (A[23..0]). Each address
bit must be latched-in on the rising edge of the DCLK. After the address is
latched in, the memory contents of the specified address are shifted out
serially on the DATA pin, beginning with the MSB. Each data bit is shifted
out on the falling edge of DCLK. The maximum DCLK frequency during
the read bytes operation is 20 MHz.
diagram for read bytes operation.
The first byte addressed can be at any location. The device automatically
increments the address to the next higher address after shifting out each
byte of data. Therefore, the device can read the whole memory with a
single read bytes operation. When the device reaches the highest address,
the address counter restarts at 0x000000, allowing the memory contents
to be read out indefinitely until the read bytes operation is terminated by
driving nCS high. The device can drive nCS high any time after data is
shifted out. If the read bytes operation is shifted in while a write or erase
cycle is in progress, the operation will not be executed. Additionally, it
will not have any effect on the write or erase cycle in progress.
2
Operation Code
3
4
Core Version a.b.c variable
5
6
7
MSB
7
8
6
9
5
10
Figure 4–11
Status Register
4
11
3
12
shows the timing
2
13
1
14
Altera Corporation
0
15
July 2004